EasyManua.ls Logo

Intel 8253 - Page 465

Intel 8253
773 pages
Print Icon
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
4/17/98 6-65 Addressing Modes and Data Types
BKPT Breakpoint
Syntax: BKPT
Operation: (PC) <-- (PC) + 1
(SSP) <-- (SSP) - 6
((SSP)) <-- (PC)
((SSP)) <-- (PSW)
(PSW) <-- code memory (bkpt vector)
(PC.15-0) <-- code memory (bkpt vector)
(PC
.23-16) <-- 0; (PC.0) <-- 0
Description: Causes a breakpoint trap. The breakpoint trap acts like an immediate interrupt, using
a vector to call a specific piece of code that will be executed in system mode. This instruction is
intended for use in emulator systems to provide a simple method of implementing hardware
breakpoints.
For a breakpoint to work properly under all conditions, it must have an instruction length no greater
than the smallest other instruction on the processor, in this case the one byte NOP. This
requirement exists because a breakpoint may be inserted in place of a NOP that is followed by
another instruction that is branched to or otherwise executed without going through the breakpoint.
If the breakpoint instruction were longer than the NOP, it would corrupt the next instruction in
sequence if that instruction were executed.
The opcode for the breakpoint instruction is specifically assigned to be all ones (FFh). This is so
that un-programmed EPROM code memory will contain breakpoints. Similarly, the NOP
instruction is assigned to opcode 00 so that both "blank" code states map to innocuous instructions.
Size: None
Flags Updated: none
5
Bytes:1
Clocks: 23/19 (PZ)
Encoding:
5. All flags are affected during the PSW load from the vector table. It is possible that these flags are restored
by the debugger, but does not have to be the case.
1 1 1 1 1 1 1 1

Table of Contents