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Intel 8253 - Page 509

Intel 8253
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4/17/98 6-109 Addressing Modes and Data Types
LSR Rd, #data4
Rd, #data5
Operation:
Bytes: 2
Clocks: For 8/16 bit shifts --> 4+1 for each 2 bits of shift
For 32 bit shifts --> 6+1 for each 2 bits of shift
Encoding: (for byte and word data sizes)
(for double word data size)
Note: SZ1/SZ0 = 00: byte operation; SZ1/SZ0 = 01: reserved; SZ1/SZ0 = 10: word operation;
SZ1/SZ0 = 11: double word operation.
CMSB0 LSB
(Rd)
d d d d #data4
1 1 0 1 SZ1 SZ0 0 0
1 1 0 1 1 1 0 0 d d d #data5

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