Intel 8253 - Page 512

XA User Guide 6-112 4/17/98
MOV [Rd+offset16], Rs
Bytes: 4
Clocks: 5
Operation: ((WS:Rd)+offset16) <-- (Rs)
Encoding:
byte 3: upper 8 bits of offset16
byte 4: lower 8 bits of offset16
MOV Rd, [Rs+]
Bytes: 2
Clocks: 4
Operation: (Rd) <-- ((WS:Rs))
(Rs) <-- (Rs) + 1 (byte operation) or 2 (word operation)
Encoding:
MOV [Rd+], Rs
Bytes: 2
Clocks: 4
Operation: ((WS:Rd)) <-- (Rs)
(Rd) <-- (Rd) + 1 (byte operation) or 2 (word operation)
Encoding:
MOV [Rd+], [Rs+]
Bytes: 2
Clocks: 6
Operation: ((WS:Rd)) <-- ((WS:Rs))
(Rs) <-- (Rs) + 1 (byte operation) or 2 (word operation)
(Rd) <-- (Rd) + 1 (byte operation) or 2 (word operation)
Encoding:
1 0 0 0 SZ 1 0 1 s s s s 1 d d d
1 0 0 0 SZ 0 1 1 d d d d 0 s s s
1 0 0 0 SZ 0 1 1 s s s s 1 d d d
1 0 0 1 SZ 0 0 0 0 d d d 0 s s s