Intel 8253 - Page 617

80C32/80C52
Rev. G (14 Jan. 97)
3
MATRA MHS
Figure 2. Pin Configuration
80C32/80C52
80C32/80C52
Diagrams are for reference only. Package sizes are not to scale.
DIL
LCC
Flat Pack
P1.4 P1.3 P1.2 P1.1/T2EX P1.0/T2 NC VCC P0.0/A0 P0.1/A1 P0.2/A2 P0.3/A3
P0.4/A4P1.5
P1.6
P1.7
RST
RxD/P3.0
NC
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
P0.5/A5
P0.6/A6
P0.7/A7
EA
NC
ALE
PSEN
P2.7/A14
P2.6/A13
P2.5/A12
WR/P3.6
RD/P3.7
XTAL2 XTAL1
VSS
NC
P2.0/A7 P2.1/A8 P2.2/A9
P2.3/A10
P2.4/A11
15
P
16
P
17
P
30
RxD/P
31
TxD/P
32
INT0/P
33
INT1/P
34
T0/P
35
T1/P
36
WR/P
37
RD/P
XTAL2 XTAL1
SS
V
NC
20
P
21
P
22
P
23
P
24
P
RST
NC
14
P
13
P
12
P
11
P
10
P
NC
CC
V
00
A0/P
/A8 /A9
/A10
/A11
/A12
04
P /A4
05
P /A5
06
P /A6
07
P /A7
EA
NC
ALE
PSEN
27
P /A15
26
P /A14
25
P /A13
/T2EX
/T2
01
A1/P
02
A2/P
03
A3/P