Intel 8253 - Page 666

4-6
6. This completes the interrupt cycle. In the AEOI mode, the
ISR bit is reset at the end of the second
INTA pulse. Oth-
erwise, the ISR bit remains set until an appropriate EOI
command is issued at the end of the interrupt subroutine.
If no interrupt request is present at step 4 of either sequence
(i.e., the request was too short in duration), the 82C59A will
issue an interrupt level 7. If a slave is programmed on IR bit
7, the CAS lines remain inactive and vector addresses are
output from the master 82C59A.
Interrupt Sequence Outputs
8080, 8085 Interrupt Response Mode
This sequence is timed by three
INTA pulses. During the first
lNTA pulse, the CALL opcode is enabled onto the data bus.
First Interrupt Vector Byte Data: Hex CD
During the second
INTA pulse, the lower address of the
appropriate service routine is enabled onto the data bus.
When interval = 4 bits, A5 - A7 are programmed, while
A0 - A4 are automatically inserted by the 82C59A. When
interval = 8, only A6 and A7 are programmed, while A0 - A5
are automatically inserted.
During the third
INTA pulse, the higher address of the appro-
priate service routine, which was programmed as byte 2 of the
initialization sequence (A8 - A15), is enabled onto the bus.
D7 D6 D5 D4 D3 D2 D1 D0
Call Code 11001101
ADDRESS BUS (16)
CONTROL BUS
DATA BUS (8)
I/OR I/OW INT INTA
CASCADE
LINES
CAS 0
CAS 1
CAS 2
SP/EN
CS RD WR INTAINTD
7
- D
0
A
0
SLAVE PROGRAM/
ENABLE BUFFER
INTERRUPT
REQUESTS
82C59A
IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ
7
6
5
4
3
2
1
0
FIGURE 5. 82C59A STANDARD SYSTEM BUS INTERFACE
CONTENT OF SECOND INTERRUPT VECTOR BYTE
IR INTERVAL = 4
D7 D6 D5 D4 D3 D2 D1 D0
7A7A6A511100
6A7A6A511000
5A7A6A510100
4A7A6A510000
3A7A6A501100
2A7A6A501000
1A7A6A500100
0A7A6A500000
IR INTERVAL = 8
D7 D6 DS D4 D3 D2 D1 D0
7A7A6111000
6A7A6110000
5A7A6101000
4A7A6100000
3A7A6011000
2A7A6010000
1A7A6001000
0A7A6000000
82C59A