Intel 8253 - Page 71

Intel387
TM
SX MATH COPROCESSOR
Encoding Clock Count Range
Instruction
Byte 0 Byte 1
Optional 32-Bit 32-Bit 64-Bit 16-Bit
Bytes 2–6 Real Integer Real Integer
DATA TRANSFER
FLD
e
Load
a
Integer/real memory to ST(0) ESC MF 1 MOD 000 R/M SIB/DISP 11–20 28–44 20–27 42– 53
Long integer memory to ST(0) ESC 111 MOD 101 R/M SIB/DISP 30–58
Extended real memory to ST(0) ESC 011 MOD 101 R/M SIB/DISP 16–47
BCD memory to ST(0) ESC 111 MOD 100 R/M SIB/DISP 49–101
ST(i) to ST(0) ESC 001 11000 ST(i) 7–12
FST
e
Store
ST(0) to integer/real memory ESC MF 1 MOD 010 R/M SIB/DISP 27–45 59–78 59 58 –76
ST(0) to ST(i) ESC 101 11010 ST(i) 7–11
FSTP
e
Store and Pop
ST(0) to integer/real memory ESC MF 1 MOD 011 R/M SIB/DISP 27–45 59–78 59 58 –76
ST(0) to long integer memory ESC 111 MOD 111 R/M SIB/DISP 64–86
ST(0) to extended real memory ESC 011 MOD 111 R/M SIB/DISP 50–56
ST(0) to BCD memory ESC 111 MOD 110 R/M SIB/DISP 116–194
ST(0) to ST(i) ESC 101 11011 ST (i) 7–11
FXCH
e
Exchange
ST(i) and ST(0) ESC 001 11001 ST(i) 10–17
COMPARISON
FCOM
e
Compare
Integer/real memory to ST(0) ESC MF 0 MOD 010 R/M SIB/DISP 15–27 36–54 18–31 39– 62
ST(i) to ST(0) ESC 000 11010 ST(i) 13–21
FCOMP
e
Compare and pop
Integer/real memory to ST(0) ESC MF 0 MOD 011 R/M SIB/DISP 15–27 36–54 18–31 39– 62
ST(i) to ST(0) ESC 000 11011 ST(i) 13–21
FCOMPP
e
Compare and pop twice
ST(1) to ST(0) ESC 110 1101 1001 13–21
FTST
e
Test ST(0) ESC 001 1110 0100 17–25
FUCOM
e
Unordered compare ESC 101 11100 ST(i) 13–21
FUCOMP
e
Unordered compare
and pop ESC 101 11101 ST(i) 13–21
FUCOMPP
e
Unordered compare
and pop twice
ESC 010 1110 1001 13–21
FXAM
e
Examine ST(0) ESC 001 1110 0101 24-37
Shaded areas indicate instructions not available in 8087/80287.
NOTE:
a. When loading single or double precision zero from memory, add 5 clocks.
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