refilled. These different situations require different actions on the part of the CPU.
d. Service the condition. Often, the interrupt service routine calls subroutines to
actually handle the cause of the interrupt. In this case the handler itself is a dispatch
routine that evaluates the cause of the interrupt and "delegates" the actual work to an
appropriate subroutine. On Motorola machines, since the ISR itself is running in
supervisor mode, any subroutines it calls will also run in supervisor mode and thus can
include instructions that would be illegal in user mode.
e. Enable interrupts if the handler disabled them in step a.
f. Restore scratch registers.
g. Execute an IRET (RTE, return from exception, on Motorola machines)
instruction. This pops the return address and FLAGS or SR back off the stack. By
popping the FLAGS or SR value, the CPU restores the condition codes that existed
before it recognized the interrupt. It also restores the original values of the control flags,
such as the trace, mode, and interrupt enable bits that processing or handling the
exception might have altered.
Obtaining the Vector Number
There are two methods of determining the vector number for software exceptions. The vector
number is a logical index into the vector table that allows the CPU to retrieve the starting address
of the exception handler. For most software-generated exceptions that are the result of error
conditions (such as divide-by-zero, overflow, address errors, privilege violations, etc.) the
circuitry that detects the error condition is also responsible for determining the vector number.
The mapping from exception to vector number is automatic, because it is hard-wired. The control
unit uses the bits of the instruction opcode itself as inputs to the circuitry that selects the proper
vector number.
The second method of obtaining the vector number also involves the bits of the instruction, but
in this case, it is not the opcode, but the operand that provides the vector number. The INT
instruction includes the interrupt number as an 8-bit immediate operand. This number is the
index into the vector table.
There are also two methods of obtaining the vector number for hardware interrupts, although
Intel chips use only one of them. Devices are either vectored, meaning the device supplies a
vector number to the CPU, or they are autovectored. Intel uses only vectored devices. We have
already seen that the 8259A selects the highest priority IRQ line currently active and places the
vector number for the attached device in an internal register. We saw earlier that the CPU sends
an interrupt acknowledge signal to the interrupt controller when it recognizes an interrupt
request. In fact, it actually sends two "pulses" on this line. The first pulse indicates that the CPU
has recognized the interrupt. The second pulse is a request for the 8259A to place the vector
number on the data bus to send it to the processor. We can summarize the Intel interrupt
acknowledge cycle (a special bus cycle, different from the normal read and write cycles) that
occurs as a response to an interrupt request as follows:
1. The CPU sets the status lines S0-S2 low (no voltage) to indicate a an interrupt
acknowledge cycle. This activates the INTA# line to the 8259A for its first pulse.
2. The 8259A sets the highest priority bit of the ISR and sends a "call" code (CDh) on the
data bus to signal that it has received the INTA# pulse and is ready to send the vector
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