normal execution state, but this time with the processor executing an interrupt handler.
We can define context switch time as the time it takes to perform a state save. Part of the state
save occurs before entering the handler, the rest occurs as a result of the first instruction(s) of the
service routine itself. More explicitly, context switch includes the following steps:
1. push the FLAGS or SR and the return address to the stack
2. set PPL2:PPL1:PPL0 to : : (this keeps the request from causing further
interrupts until the device actually removes the source of the interrupt) or set the ISR
3. clear the trace bit and, on the Motorola chip, set the mode bit of the SR to 1
4. obtain the vector number so that the CPU can retrieve the address of the service routine
5. execute the first instruction(s) of the service routine to save scratch registers and
(optionally), to disable interrupts
Context switch time is one component necessary to understanding another important concept for
exception processing: interrupt latency. We can define interrupt latency as the time elapsed from
the appearance of the interrupt to the time that the processor starts to execute the handler. It
should be plain to you that the shorter interrupt latency is, the better performance will be. The
maximum interrupt latency that can occur depends on at least two factors. First and most obvious
is context switch time itself. The second factor is also fairly obvious if we realize that the
microprocessor only recognizes hardware interrupts (with the exception of NMIs) between
instructions. That means that if a device generates an interrupt just as the execution of an
instruction is beginning, it will have to wait until execution is complete before the CPU will
recognize it. Thus, in the simplest case, we can define the maximum interrupt latency possible
(and thus the worst performance possible) as:
WWWWMax Latency = execution time of slowest machine instruction + context switch time
It may not be quite this simple to define maximum interrupt latency, however. If we allow
processes or service routines to temporarily disable interrupts, the latency times may stretch out
considerably, since we also have to add the time for which interrupts are disabled. Thus a more
complete definition of maximum interrupt latency would be:
WWWWMax Latency = execution time of slowest machine instruction + context switch time +
maximum amount of time that interrupts are disabled
Communication Between I/O Devices and the CPU
Typically, I/O devices require additional hardware in the form of a controller or interface (often
an expansion card in the machine or a chip on the device itself or on the motherboard) to make
up the peripheral interface to resolve timing and format differences between the device and CPU.
For example, a keyboard has one line connected to each key. When you press a key, the wire
connected to that key carries voltage (the line is activated). To be useful to the CPU, this voltage
must be translated to an ASCII code. The translation is the task of the encoder/controller.
To Next Page
Loading...