Intel Pentium 4 User Manual

Introduction
R
4 Intel
®
Pentium
®
4 Processor / Intel
®
850 Chipset Family Platform Design Guide
4.3.3
Rambus DRCG* to Direct Rambus Channels (400 MHz Clocks)......... 49
4.3.3.1 Trace Lengths...................................................................... 50
4.3.3.2 Topology Considerations ..................................................... 52
4.3.3.3 Rambus RDRAM* Device ClockTermination ...................... 52
4.3.4 Rambus DRCG* Impedance Matching Circuit...................................... 54
4.3.5 Rambus DRCG* Layout Example......................................................... 55
4.4 Routing Guidelines for 66 MHz and 33 MHz Clocks ............................................ 56
4.4.1 66 MHz / 33 MHz Clock Relationships.................................................. 56
4.4.2 66 MHz Clock Routing Length Guidelines ............................................ 57
4.4.2.1 3V66 Clock Routing Requirement for Intel
®
82850E
Platforms ............................................................................. 57
4.4.3 33 MHz Clock Routing Length Guidelines ............................................ 58
5 System Bus Routing.......................................................................................................... 61
5.1 Return Path........................................................................................................... 62
5.2 GTLREF Layout and Routing Recommendations ................................................ 63
5.3 Processor Configuration ....................................................................................... 64
5.3.1 Topology and Routing ........................................................................... 64
5.3.1.1 Design Recommendations .................................................. 65
5.3.1.2 Design Considerations......................................................... 66
5.4 Routing Guidelines for Asynchronous GTL+ and Other Signals .......................... 71
5.4.1 Topologies............................................................................................. 72
5.4.1.1 Topology 1: Asynchronous GTL+ Signals Driven by the
Processor ............................................................................ 72
5.4.1.2 Topology 2: Asynchronous GTL+ Signals Driven by Intel
®
ICH2..................................................................................... 73
5.4.1.3 Topology 2A: INIT#.............................................................. 74
5.4.1.4 Topology 2B: Asynchronous GTL+ Signals Driven by Intel
®
ICH2..................................................................................... 75
5.4.1.5 Topology 3: VCCIOPLL, VCCA and VSSA.......................... 75
5.4.1.6 Topology 4: BR0# and RESET# .......................................... 76
5.4.1.7 Topology 5: COMP[1:0] Signals .......................................... 76
5.4.1.8 Topology 6a: BSEL[1:0] Termination – 400 MHz System Bus
Only ..................................................................................... 76
5.4.1.9 Topology 6b: BSEL[1:0] Termination – 533/400 MHz System
Bus....................................................................................... 76
5.4.1.10 Topology 7: THERMDA/THERMDC Routing Guidelines..... 77
5.4.1.11 Topology 8: TESTHI and RESERVED Pins ........................ 77
5.4.1.12 Topology 9: Processor Voltage Regulator Sequencing
Requirements ...................................................................... 78
5.4.1.13 VCCVID Regulator Recommendations ............................... 78
5.4.1.14 Topology 10: THERMTRIP# Power Down Circuit ............... 80
5.5 Intel
®
MCH System Bus Interface......................................................................... 82
5.5.1 Intel
®
MCH System Bus I/O Decoupling Requirements ........................ 83
5.6 System Bus Routing Guidelines - Four-Layer Motherboard................................. 85
5.6.1 Processor Power Delivery..................................................................... 87
6 Memory Interface Routing ................................................................................................. 89
6.1 Rambus RDRAM* Device Routing Guidelines ..................................................... 90
6.1.1 Rambus Signaling Level (RSL) Signals ................................................ 91
6.1.2 Rambus* Signaling Level (RSL) Channel Compensation..................... 94
6.1.2.1 Package Trace Compensation (RSL and Clocking Signals)94
6.1.2.2 Via Compensation ............................................................... 95

Intel Pentium 4 Specifications

General

Architecture	x86
Core Count	1
Microarchitecture	NetBurst
Manufacturer	Intel
Core Names	Willamette, Northwood, Prescott, Cedar Mill
Virtualization Technology	No
Release Date	November 20, 2000
Clock Speed	1.3 GHz to 3.8 GHz
FSB Speed	400 MHz to 1066 MHz
Socket	Socket 423, Socket 478, LGA 775
Introduced	2000
Product Line	Pentium
Front Side Bus	400 MHz to 1066 MHz
Hyper-Threading	Yes (Prescott and later)
64-bit Support	Yes (Prescott and later)
Instruction Set	MMX, SSE, SSE2, SSE3
Discontinued	2008
Process Technology	180 nm, 130 nm, 90 nm, 65 nm
L2 Cache	256 KB, 512 KB, 1 MB, 2 MB
Lithography	180 nm, 130 nm, 90 nm, 65 nm
L1 Cache	8 KB