Intel Pentium 4 User Manual

Introduction
R
Intel
®
Pentium
®
4 Processor / Intel
®
850 Chipset Family Platform Design Guide 5
6.1.2.3
Differential Clock Compensation ......................................... 96
6.1.2.3.1 Non-Differentially Routed Clocks – 533 MHz
Rambus RDRAM* Technology ............................ 97
6.1.2.4 Signal Layer Alternation for Rambus RIMM Connector Pin
Compensation ..................................................................... 98
6.1.2.5 Rambus RIMM Connector Impedance Compensation........ 98
6.1.3 RSL Signal Termination ...................................................................... 102
6.1.4 Rambus RDRAM* Device Reference Voltage .................................... 104
6.1.5 High-Speed CMOS Routing ................................................................ 105
6.1.6 SIO Routing......................................................................................... 105
6.1.7 Suspend-to-RAM Shunt Transistor ..................................................... 107
6.1.8 Rambus RDRAM* Device Channel Margin Improvement .................. 108
6.1.9 533 MHz (PC1066) Rambus RIMM Module Thermal Consideration.. 109
6.2 Rambus Technology Routing Guidelines - Four-Layer Motherboard ................. 110
6.2.1 Optimized Rambus RDRAM* Device Routing Rules for a Four-Layer
Motherboard Design............................................................................ 112
7 AGP Interface Routing .................................................................................................... 113
7.1 AGP Routing Guidelines..................................................................................... 114
7.1.1 1X Timing Domain Signal Routing Guidelines .................................... 114
7.1.2 2X/4X Timing Domain Signal Routing Guidelines............................... 114
7.1.2.1 Trace Lengths Less Than 6 Inches ................................... 114
7.1.2.2 Trace Lengths Greater Than 6 Inches and Less Than 7.25
Inches ................................................................................ 115
7.1.3 AGP Interfaces Trace Length Summary............................................. 116
7.1.4 I/O Decoupling Guidelines .................................................................. 117
7.1.5 Signal Power/Ground Referencing Recommendations ...................... 118
7.1.6 VDDQ and TYPEDET# ....................................................................... 118
7.1.7 V
REF
Generation .................................................................................. 118
7.1.8 Intel
®
MCH AGP Interface Buffer Compensation................................ 119
7.1.9 AGP Pull-ups/Pull-down on AGP Signals ........................................... 119
7.1.10 AGP Signal Voltage Tolerance List..................................................... 121
7.1.11 AGP Connector ................................................................................... 121
7.2 AGP Universal Retention Mechanism (RM) ....................................................... 121
7.3 AGP Routing Guidelines - Four-Layer Motherboard........................................... 124
8 Hub Interface Routing ..................................................................................................... 127
8.1 Hub Interface Routing Guidelines....................................................................... 127
8.2 8-Bit Hub Interface Routing Guidelines .............................................................. 128
8.2.1 8-Bit Hub Interface Data Signals......................................................... 128
8.2.2 8-Bit Hub Interface Strobe Signals...................................................... 128
8.2.3 8-Bit Hub Interface HIREF Generation/Distribution ............................ 128
8.2.4 8-Bit Hub Interface Compensation...................................................... 130
8.2.5 8-Bit Hub Interface Decoupling Guidelines ......................................... 130
8.3 Hub Interface Routing Guidelines - Four-Layer Motherboard ............................ 131
9 I/O Controller Hub 2 ........................................................................................................ 133
9.1 This Chapter Provides Information on the Intel
®
82801BA I/O Controller Hub 2
(ICH2) IDE Interface ........................................................................................... 133
9.1.1 IDE Cable............................................................................................ 133
9.1.2 Cable Detection for Ultra ATA/66 and Ultra ATA/100 ......................... 134
9.1.2.1 Combination Host-Side/Device-Side Cable Detection....... 135
9.1.2.2 Device-Side Cable Detection............................................. 136

Intel Pentium 4 Specifications

General

Architecture	x86
Core Count	1
Microarchitecture	NetBurst
Manufacturer	Intel
Core Names	Willamette, Northwood, Prescott, Cedar Mill
Virtualization Technology	No
Release Date	November 20, 2000
Clock Speed	1.3 GHz to 3.8 GHz
FSB Speed	400 MHz to 1066 MHz
Socket	Socket 423, Socket 478, LGA 775
Introduced	2000
Product Line	Pentium
Front Side Bus	400 MHz to 1066 MHz
Hyper-Threading	Yes (Prescott and later)
64-bit Support	Yes (Prescott and later)
Instruction Set	MMX, SSE, SSE2, SSE3
Discontinued	2008
Process Technology	180 nm, 130 nm, 90 nm, 65 nm
L2 Cache	256 KB, 512 KB, 1 MB, 2 MB
Lithography	180 nm, 130 nm, 90 nm, 65 nm
L1 Cache	8 KB