Introduction
R
Intel
®
Pentium
®
4 Processor / Intel
®
850 Chipset Family Platform Design Guide 9
16.2
CK00 Routing Guidelines ................................................................................... 274
16.2.1 CK00 Clocking .................................................................................... 274
16.3 RAMBUS Technology Routing Guidelines ......................................................... 276
16.3.1 RSL Signals ........................................................................................ 276
16.3.2 Ground Isolation.................................................................................. 278
16.3.3 V
term
Layout ......................................................................................... 279
16.3.4 Rambus DRCG* Clock Routing Recommendation............................. 280
16.3.5 Rambus DRCG* Layout (Clean Power Supply) .................................. 281
16.3.6 Rambus DRCG* (CTM/CTM# Output Network Layout)...................... 282
16.3.7 RAMREF Routing................................................................................ 282
16.4 AGP Guidelines .................................................................................................. 282
16.4.1 All 1X Signals ...................................................................................... 282
16.4.2 2X/4X Signals...................................................................................... 283
16.4.2.1 AGP Less Than 6 Inches................................................... 283
16.4.2.2 AGP Interface Greater Than 6 Inches and Less Than 7.25
Inches ................................................................................ 284
16.4.3 Intel
®
MCH AGP Decoupling............................................................... 284
16.4.4 AGP Connector Decoupling................................................................ 285
16.5 8 Bit Hub Interface.............................................................................................. 285
16.5.1 Hub Decoupling................................................................................... 285
16.6 IDE Interface....................................................................................................... 286
16.7 CNR.................................................................................................................... 286
16.8 Intel
®
AC’97 ........................................................................................................ 286
16.9 USB .................................................................................................................... 287
16.10 Intel
®
ICH2 Decoupling ....................................................................................... 287
16.11 RTC ............................................................................................................ 288
16.12 LAN* Connect Interface...................................................................................... 288
16.13 Miscellaneous ..................................................................................................... 289
Appendix A: Reference Schematics ....................................................................................................... 291