Intel Pentium 4 User Manual

Introduction
R
8 Intel
®
Pentium
®
4 Processor / Intel
®
850 Chipset Family Platform Design Guide
12
Power Distribution Guidelines ......................................................................................... 229
12.1 Definitions ........................................................................................................... 229
12.2 Power Management ........................................................................................... 229
12.2.1 ACPI Hardware Model ........................................................................ 230
12.2.2 Thermal Design Power ....................................................................... 230
12.3 1.8 V RAC Isolation Solution .............................................................................. 231
12.4 Vterm/Vdd Power Sequencing Requirement...................................................... 234
12.5 Intel
®
850 Chipset Power Sequencing Requirements ........................................ 235
12.6 Intel
®
ICH2 V5REF and Vcc3.3 Sequencing Requirement................................. 236
12.7 CPU / CK00 Power Sequencing Requirement ................................................... 237
13 Debug Port Routing Guidelines....................................................................................... 239
14 Debug Tools Specifications............................................................................................. 241
14.1 Logic Analyzer Interface (LAI) ............................................................................ 241
14.1.1 Mechanical Considerations................................................................. 241
14.1.2 Electrical Considerations..................................................................... 241
15 Schematic Review Checklist ........................................................................................... 243
15.1 Processor Checklist (All Signals)........................................................................ 243
15.2 CK00 Clock Generator Checklist........................................................................ 248
15.3 Direct Rambus Clock Generator (DRCG1 and DRCG2) Checklist .................... 249
15.4 Intel
®
850 Chipset Checklist ............................................................................... 251
15.5 AGP Checklist .................................................................................................... 253
15.6 Rambus RIMM* Connector Checklist................................................................. 255
15.7 Intel
®
ICH2 Checklist .......................................................................................... 259
15.7.1 PCI Interface ....................................................................................... 259
15.7.2 Hub Interface ...................................................................................... 260
15.7.3 LAN* Interface..................................................................................... 260
15.7.4 EEPROM Interface ............................................................................. 260
15.7.5 FWH/LPC Interface............................................................................. 261
15.7.6 Interrupt Interface................................................................................ 261
15.7.7 GPIO ................................................................................................... 262
15.7.8 USB..................................................................................................... 263
15.7.9 Power Management ............................................................................ 263
15.7.10 Processor Signals ............................................................................... 263
15.7.11 System Management .......................................................................... 264
15.7.12 RTC ........................................................................................... 264
15.7.13 Intel
®
AC’97......................................................................................... 265
15.7.14 Miscellaneous Signals......................................................................... 265
15.7.15 Power ........................................................................................... 266
15.7.16 IDE Interface ....................................................................................... 267
16 Layout Review Checklist ................................................................................................. 269
16.1 Processor and System Bus ................................................................................ 269
16.1.1 AGTL+ Signals.................................................................................... 269
16.1.2 Asynchronous GTL+ and Other Signals ............................................. 271
16.1.3 Processor Keep-Out Zones ................................................................ 271
16.1.4 Processor Decoupling......................................................................... 272
16.1.5 Intel
®
82850 MCH Decoupling ............................................................ 272
16.1.6 AGTL+ ( V
REF
HDVREF [3:0], HAVREF [1:0] and CCVREF).............. 273

Intel Pentium 4 Specifications

General

Architecture	x86
Core Count	1
Microarchitecture	NetBurst
Manufacturer	Intel
Core Names	Willamette, Northwood, Prescott, Cedar Mill
Virtualization Technology	No
Release Date	November 20, 2000
Clock Speed	1.3 GHz to 3.8 GHz
FSB Speed	400 MHz to 1066 MHz
Socket	Socket 423, Socket 478, LGA 775
Introduced	2000
Product Line	Pentium
Front Side Bus	400 MHz to 1066 MHz
Hyper-Threading	Yes (Prescott and later)
64-bit Support	Yes (Prescott and later)
Instruction Set	MMX, SSE, SSE2, SSE3
Discontinued	2008
Process Technology	180 nm, 130 nm, 90 nm, 65 nm
L2 Cache	256 KB, 512 KB, 1 MB, 2 MB
Lithography	180 nm, 130 nm, 90 nm, 65 nm
L1 Cache	8 KB