Lattice Semiconductor CertusPro-NX - Page 112

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
112 © 2020-2021 Lattice Semiconductor FPGA-TN-02245-0.81
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Attribute
Selectable Values
Default
Dependency on Other Attributes
name followed by suffix “_PCSGRP”.
Always uneditable.
Mode
“Rx_only”, “Tx_only”,
“Rx_and_Tx”
“Rx_and_Tx”
If Protocol == “PCIE”, value is “Rx and
Tx”;
If Protocol == “RXAUI”, value is “Rx
and Tx”;
If Protocol == “SLVS_EC”, value is “Rx
only”.
Data Rate (Gbps)
Uneditable.
6.25
Available if one of these conditions is
true:
Protocol != “SLVS_EC”
Protocol != “COAXPRESS”
Protocol != “DP”
Protocol != “EDP”
Protocol != “PCIE”
Protocol != “PCIE-PCS”
Rate0 (Gbps)
See Table 7.5
N/A
Available if one of these conditions is
true:
Protocol == “SLVS_EC”
Protocol == “COAXPRESS”
Protocol == “DP”
Protocol == “EDP”
Protocol == “PCIE”
Protocol == “PCIE-PCS”
Rate1 (Gbps)
See Table 7.5
N/A
Available if one of these conditions is
true:
Protocol == “SLVS_EC”
Protocol == “COAXPRESS”
Protocol == “DP”
Protocol == “EDP”
Protocol == “PCIE”
Protocol == “PCIE-PCS”
Rate2 (Gbps)
See Table 7.5
N/A
Available if one of these conditions is
true:
Protocol == “SLVS_EC”
Protocol == “COAXPRESS”
Protocol == “DP”
Protocol == “EDP”
Protocol == “PCIE”
Protocol == “PCIE-PCS”
Select Default Rate
See Table 7.5
N/A
Available if one of these conditions is
true:
Protocol == “SLVS_EC”
Protocol == “COAXPRESS”
Protocol == “DP”
Protocol == “EDP”
Bus Width
See Table 7.5
20
Uneditable.
Ref Clk Freq (MHz)
See Table 7.5
156.25
Uneditable.
Use internal REFCLK
“Checked”, “Unchecked”
“Unchecked”
—
RefClk Selection for Quad0
“PLL Clock 0”,
“PLL Clock 1”,
“External IO Pad”,
“PCS Clock”
“PLL Clock 0”
Active if Use internal REFCLK ==
“Checked”