Lattice Semiconductor CertusPro-NX - Table A. 7. Tx PLL M & N Settings [Reg05]; Table A. 8. Rx PLL F Settings and PCLK Ratio [Reg06]

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
124 © 2020-2021 Lattice Semiconductor FPGA-TN-02245-0.81
All rights reserved. CONFIDENTIAL
Field
Name
Access
Width
Reset
Description
Divider). PCLK is used by the PCIe PCS logic as well as by
the majority of the PMA control logic, and thus is also
useful for other protocol in order to reduce the amount of
logic requiring high TxClk frequency.
2’b11 – divided by 4
2’b10 – divided by 2
2’b00 – divided by 1
[3:0]
TxF
RW
4
4’h4
Defines the Tx PLL F setting.
4’b0101 – 6
4’b0100 – 5
4’b0011 – 4
4’b0010 – 3
4’b0001 – 2
4’b0000 – 1
Note: This register can be reprogrammed when the PHY is under reset or when both CDR PLL and Tx PLL are under reset.
Table A. 7. Tx PLL M & N Settings [reg05]
Field
Name
Access
Width
Reset
Description
[7]
cnt250ns_max
RSVD
1
1’b0
Internal usage.
[6:5]
TxM
RW
2
2’b10
Defines the Tx PLL M setting.
2’b11 – 8
2’b10 – 4
2’b01 – 2
2’b00 – 1
[4:0]
TxN
RW
5
5’h04
Defines the Tx PLL N setting.
5’b10011 – 20
5’b01111 – 16
5’h01001 – 10
5’b00111 – 8
5’b00100 – 5
Note: This register can be reprogrammed when the PHY is under reset or when Tx PLL is under reset.
Table A. 8. Rx PLL F Settings and PCLK Ratio [reg06]
Field
Name
Access
Width
Reset
Description
[7:6]
reserved
RSVD
2
2’b00
—
[5:4]
rx_div_mode0
RW
2
2’b10
Defines the ratio between internal Rx CLK and RxClk (PMA
Clock Divider).
2’b11 – divided by 4
2’b10 – divided by 2
2’b00 – divided by 1
[3:0]
TxF
RW
4
4’h4
Defines the Tx PLL F setting.
4’b0101 – 6
4’b0100 – 5
4’b0011 – 4
4’b0010 – 3
4’b0001 – 2
4’b0000 – 1
Note: This register can be reprogrammed when the PHY is under reset or when CDR PLL is under reset.