CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
FPGA-TN-02245-0.81 © 2020-2021 Lattice Semiconductor 95
All rights reserved. CONFIDENTIAL
64B/66B PCS Loopback
Figure 9.4 shows three loopback modes implemented by 64B/66B PCS: Loopback Path A, Loopback Path B and
Loopback Path C.
In loopback path A mode, the 16-bit input data of Rx path comes from Tx path. In addition, the tx_pcs_clk is used to
drive both Tx path and Rx path. The Loopback FIFO is used for clock phase compensation between Tx path and Rx path.
This mode can be enabled or disabled by the bit[0] of MPCS register rege0 when MPCS works as 64B/66B PCS mode.
In loopback path B mode, the Tx XGMII 64-bit data and 8-bit control from fabric are fed back to Rx FIFO directly. This
mode can be enabled or disabled by the bit[2] of MPCS register rege0 when MPCS works as 64B/66B PCS mode.
In loopback path C mode, the received XGMII 64-bit data and 8-bit control from Rx path are fed back to Tx FIFO
directly. This mode can be enabled or disabled by the bit[1] of MPCS register rege0 when MPCS works as 64B/66B PCS
mode.
Figure 9.4. 64B/66B PCS Loopback Mode
PMA Only Loopback
The PMA Only mode, same as 8B/10B PCS, also supports loopback modes. The near end parallel loopback mode can be
enabled or disabled by the bit[0] of MPCS register rege0 when MPCS works as PMA Only mode. The far end parallel
loopback mode can be enabled or disabled by the bit [1] of MPCS register rege0 when MPCS works as PMA Only mode.
Signal Detector
Each channel contains a signal detector circuit at receiver input, as shown in Figure 9.5. Signal detector picks up the
data signal from channel receiver input, and compares its differential amplitude with the threshold voltage. If the input
signal differential amplitude is higher than the threshold voltage, the detector asserts the TranDet output.
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