Lattice Semiconductor CertusPro-NX Usage Guide

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
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All rights reserved. CONFIDENTIAL
Other Signals
Table 5.11 shows signals other than MPCS, EPCS, PIPE and LMMI interfaces per quad. NL means the number of lanes.
For detailed descriptions about Quad-to-Quad signals, refer to the Clocks and Reset section.
Table 5.11. Other Signals
Port Name
I/O
Width
Description
PMA Serial I/O
1
sdq_refclkp_i
In
1
Reference Clock of SerDes PLL in one Quad.
sdq_refclkn_i
In
1
Reference Clock of SerDes PLL in one Quad.
sd[n]rxp_i
In
NL
Analog Rx differential IO.
sd[n]rxn_i
In
NL
Analog Rx differential IO.
sd[n]txp_o
Out
NL
Analog Tx differential IO.
sd[n]txn_o
Out
NL
Analog Tx differential IO.
sd[n]_rext_i
In
NL
External Resistance.
sd[n]_refret_i
In
NL
Analog reference return for PMA PLL.
Reference Clock
sd_ext_0_refclk_i
In
1
Reference Clock from SD_EXT0_REFCLKP, SD_EXT0_REFCLKN.
sd_ext_1_refclk_i
In
1
Reference Clock from SD_EXT1_REFCLKP, SD_EXT1_REFCLKN.
pll_0_refclk_i
In
1
Reference Clock from left top GPLL.
pll_1_refclk_i
In
1
Reference Clock from right top GPLL.
sd_pll_refclk_i
In
1
Reference Clock from FPGA Fabric, only for test purpose.
diffioclksel_i
In
1
Dynamic clock source selection:
1’b1 – sd_ext_1_refclk_i.
1’b0 – sd_ext_0_refclk_i.
clksel_i
In
2
Dynamic clock source selection:
2’b11 – sd_pll_refclk_i.
2’b10 – sd_ext_0_refclk_i or sd_ext_1_refclk_i.
2’b01 – pll_1_refclk_i.
2’b00 – pll_0_refclk_i.
use_refmux_i
In
1
Dynamic clock source selection:
1’b1 – clock from PCSREFMUX output.
1’b0 – clock from per quad source (sdq_refclkp_i,
sdq_refclkn_i).
Quad-Quad Interface
tx_lalign_clk_out_o
Out
1
The outputted clock for sharing among Quads are hooked up
during Quad integration.
rx_lalign_clk_out_o
Out
1
The outputted clock for sharing among Quads are hooked up
during Quad integration.
tx_lalign_clk_in_i
In
1
The input clock is shared by all channels within a Quad to
implement lane alignment.
rx_lalign_clk_in_i
In
1
The input clock is shared by all channels within a Quad to
implement lane alignment.
lalign_out_up_o
Out
8
The connection signals between Quads for lane alignment
across Quad boundary.
lalign_in_up_i
In
8
The connection signals between Quads for lane alignment
across Quad boundary.
lalign_out_down_o
Out
8
The connection signals between Quads for lane alignment
across Quad boundary.
lalign_in_down_i
In
8
The connection signals between Quads for lane alignment
across Quad boundary.
JTAG Interface
acjtag_mode_i
In
1
When asserted, this signal activates the ACJTAG controller of

Lattice Semiconductor CertusPro-NX Specifications

General

Brand	Lattice Semiconductor
Model	CertusPro-NX
Category	Computer Hardware
Language	English