Lattice Semiconductor CertusPro-NX Usage Guide

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
FPGA-TN-02245-0.81 © 2020-2021 Lattice Semiconductor 69
All rights reserved. CONFIDENTIAL
TX FIFO
/2,
/1
tx_pcs_clk
tx_lalign_clk
Tx Path
Rx Path
Tx Lane-to-lane
Deskew
RX FIFO
tx_pcs_clka
tx_pcs_clkb
tx_out_clk
tx_usr_clk
rx_out_clk
rx_usr_clk
rx_pcs_clk
Fabric
/2,
/1
PMA Controller
Figure 6.30. PMA Only Mode Block Diagram
6.4.3.1. Data Bus Description
The bit mapping of user logic data bus to PMA data bus is shown in Table 6.7.
Table 6.7. PMA Only Mode Data Bus
PMA Data
Bus Width
Mode
MPCS Internal
Data Bus Width
Gearing
MPCS-Fabric Data Bus
Mapping
1
Transfer Ordering
2,3
20-bit
Mode 1-a
20-bit
1:1
usr_dbus[19:0]
T0: usr_dbus[19:0]
Mode 1-b
2:1
usr_dbus[39:0]
T0: usr_dbus[19:0]
T1: usr_dbus[39:20]
10-bit
Mode 2-a
10-bit
1:1
usr_dbus[9:0]
T0: usr_dbus[9:0]
Mode 2-b
2:1
usr_dbus[19:0]
T0: usr_dbus[9:0]
T1: usr_dbus[19:0]
Mode 2-c
20-bit
1:1
usr_dbus[19:0]
T0: usr_dbus[9:0]
T1: usr_dbus[19:0]
Mode 2-d
2:1
usr_dbus[39:0]
T0: usr_dbus[9:0]
T1: usr_dbus[19:10]
T2: usr_dbus[29:20]
T3: usr_dbus[39:30]
5-bit
Mode 3-a
10-bit
1:1
usr_dbus[9:0]
T0: usr_dbus[4:0]
T1: usr_dbus[9:5]
Mode 3-b
2:1
usr_dbus[19:10]
T0: usr_dbus[4:0]
T1: usr_dbus[9:5]
T2: usr_dbus[14:10]
T3: usr_dbus[19:15]
16-bit
Mode 4-a
16-bit
1:1
usr_dbus[15: 0]
T0: usr_dbus[15:0]
Mode 4-b
2:1
usr_dbus[35: 20]
usr_dbus[15: 0]
T0: usr_dbus[15:0]
T1: usr_dbus[35:20]
8-bit
Mode 5-a
8-bit
1:1
usr_dbus[7:0]
T0: usr_dbus[7:0]
Mode 5-b
2:1
usr_dbus[17:10]
usr_dbus[7:0]
T0: usr_dbus[7:0]
T1: usr_dbus[17:10]
Notes:

Lattice Semiconductor CertusPro-NX Specifications

General

Brand	Lattice Semiconductor
Model	CertusPro-NX
Category	Computer Hardware
Language	English