Lattice Semiconductor CertusPro-NX - Serdes;Pcs Register Access; Register Access Bus; Figure 10.1. Burst Read Transaction; Figure 10.2. Back-To-Back Read and Write Transaction

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
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SerDes/PCS Register Access
Register Access Bus
Each SerDes/PCS channel has independent register access bus: Lattice Memory Mapped Interface (LMMI). It has the
following features:
 8-bit width of write and read data.
 9-bit address (offset), the highest bit is used to select register space.
offset[8] == 1’b1, MPCS register space
offset[8] == 1’b0, PMA register space
 Support single byte read and write.
 Support burst read and write.
 Read-back data validity indication.
 Ready signal to support wait state.
When the LMMI master is ready to request a transaction, it asserts lmmi_request_i and drives the request data
(lmmi_wr_rdn_i, lmmi_offset_i, and lmmi_wdata_i) at the same time and starts sampling lmmi_ready_o on the
positive edge clock. The LMMI master holds the lmmi_request_i and the requested data constantly until the
lmmi_ready_o is asserted. When both lmmi_request_i and lmmi_ready_o are asserted on the same positive clock
edge, the LMMI slave latches the requested data and starts transaction. Once the requested data has been latched, the
LMMI master can immediately start the next transaction request as its own discretion. If the LMMI slave is ready to
start another transaction in the next clock cycle, it holds lmmi_ready_o asserted. Otherwise, the LMMI slave de-asserts
lmmi_ready_o until it is ready to accept a new transaction. Figure 10.1, Figure 10.2, and Figure 10.3 show the examples
for different transactions.
Figure 10.1. Burst Read Transaction
Figure 10.2. Back-to-Back Read and Write Transaction