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Page 88 (Figure 7.20. EPCS Mode Reset Sequence (Tx Path))
Lattice Semiconductor CertusPro-NX - Figure 7.20. EPCS Mode Reset Sequence (Tx Path); Figure 7.21. EPCS Mode Reset Sequence (Rx Path)
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CertusPro-NX SerDes/PCS Usage Guide
Preliminary
Technical Note
88
©
2020-
2021
Lattice Semiconductor
FPGA-
TN
-
02245
-0.81
All rights reserved. CONFI
DENTIAL
Figure 7.
20
.
EP
CS Mode Reset Seq
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Figure 7.
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CS Mode Reset Seq
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89
Table of Contents
Main Page
Table of Contents
3
Glossary
11
Introduction
14
Features
15
Using this Technical Note
16
Standards Supported
17
Table 4.1. Standards Supported by the Serdes/Pcs
17
Architecture Overview
18
Device Architecture
18
Figure 5.1. Certuspro-NX 100K Device Block Diagram
18
Serdes/Pcs Architecture
19
Table 5.1. Maximum Number of Serdes/Pcs Channels Per Certuspro-NX Device
19
Table 5.2. Maximum Number of PCI Express Blocks Per Certuspro-NX Device
19
PCI Express Architecture
20
Figure 5.2. Certuspro-NX Serdes/Pcs Quad Architecture
20
Table 5.3. Block Usage for the Corresponding Serdes/Pcs Mode
20
Figure 5.3. PCI Express Hard IP Architecture
21
Table 5.4. PCI Express Link Layer Quad Lane Mapping
21
MPCS Architecture
22
Figure 5.4. PCI Express Link Layer Functional Diagram
22
Figure 5.5. MPCS Quad Block Diagram
22
Figure 5.6. MPCS Channel Functional Block Diagram
23
Reference Clock Architecture
24
Figure 5.7. Certuspro-NX 100K Device Serdes Reference Clock Architecture
24
Table 5.5. 10GBASE-R Lane Mapping
24
Multi-Protocol Design Consideration
25
Serdes/Pcs Block Signal Interface
25
Figure 5.8. PCI Express Hard IP Mode
25
Table 5.6. Certuspro-NX Mixed Protocols Within a Quad
25
Figure 5.9. PIPE Mode
26
Figure 5.10. MPCS Mode
26
Detailed Interface Descriptions
27
Figure 5.11. PMA Only Mode
27
Table 5.7. MPCS Interface
27
Table 5.8. EPCS Interface
30
Table 5.9. PIPE Interface
31
Table 5.10. LMMI Interface
37
Table 5.11. Other Signals
38
Table 5.12. Data Bus Sharing and Mapping
39
Control and Status Signals
43
Table 5.13. Control and Status Signals Functions (8B/10B PCS)
43
Table 5.14. Control and Status Signals Functions (64B/66B PCS)
43
Detailed Channel Block Diagram
44
Figure 5.12. Detailed Channel Block Diagram of MPCS-8B/10B Mode
45
Figure 5.13. Detailed Channel Block Diagram of MPCS-64B/66B Mode
45
Figure 5.14. Detailed Channel Block Diagram of MPCS-PMA Only Mode
46
Serdes/Pcs Function Description
47
Serdes (PMA)
47
Figure 6.1. Simplified Block Diagram of the Serdes (PMA)
47
Figure 6.2. PCI Express AC Coupling Capacitors Location
48
Table 6.1. Operation Range for F
48
PMA Controller
49
PCI Express PCS
49
Figure 6.3. PMA Controller Block Diagram
49
Mpcs
50
Figure 6.4. PCI Express PCS & PMA Controller Block Diagram
50
Figure 6.5. MPCS 8B/10B PCS Block Diagram
50
Table 6.2. Bit Mapping of Tx Data Bus
51
Table 6.3. Bit Mapping of Rx Data Bus
52
Figure 6.6. Tx Gearing Case I
53
Figure 6.7. Tx Gearing Case II
54
Figure 6.8. Rx Gearing Case I
54
Table 6.4. Tx FIFO Usage
54
Figure 6.9. Rx Gearing Case II
55
Figure 6.10. Byte Shifting for Word Alignment Pattern
55
Table 6.5. Disparity Combinations
55
Figure 6.11. Word Aligner Block Diagram
57
Figure 6.12. Link Synchronization FSM
58
Table 6.6. Example Settings for XAUI and Gige
58
Figure 6.13. before 2-Byte Boundary Alignment
59
Figure 6.14. after 2-Byte Boundary Alignment
59
Figure 6.15. Data Stream before Word Alignment
60
Figure 6.16. Data Stream after Word Alignment
60
Figure 6.17. Bit Mapping of Input Data
60
Figure 6.18. the Expected Location of Synchronization Code
61
Figure 6.19. SKIP Pattern Format
61
Figure 6.20. SKIP Pattern Mask Code
62
Figure 6.21. FIFO High/Low Water Line
62
Figure 6.22. Lane Alignment Pattern Mask Code
63
Figure 6.23. Data Shifting for Alignment
63
Figure 6.24. 64B/66B PCS Channel Block Diagram
64
Figure 6.25. XGMII Vs. MPCS-Fabric Interface
65
Figure 6.26. 64B/66B PCS Tx FIFO Write Operation Case I
66
Figure 6.27. 64B/66B PCS Tx FIFO Write Operation Case II
67
Figure 6.28. 64B/66B PCS Rx FIFO Read Operation Case I
67
Figure 6.29. 64B/66B PCS Rx FIFO Read Operation Case II
67
Figure 6.30. PMA Only Mode Block Diagram
69
Table 6.7. PMA Only Mode Data Bus
69
Quad Common
70
Reference Clock
70
Table 6.8. Channel Alignment Within One Quad
70
Table 6.9. Channel Alignment between Two Quads
70
Figure 6.31. Quad Reference Clock Source
71
Clocks and Reset
72
MPCS Channel Clock Detail
72
Figure 7.1. 8B/10B PCS Channel Clock Diagram
72
Table 7.1. 8B/10B PCS Channel Clock
72
Figure 7.2. 64B/66B PCS Channel Clock Diagram
73
Table 7.2. 64B/66B PCS Channel Clock
74
Figure 7.3. PMA Only Mode Clock Diagram
75
Table 7.3. PMA Only Mode Channel Clock
75
MPCS Quad Clock Detail
76
Figure 7.4. Quad Clock Distribution Diagram
76
MPCS Quad-To-Quad Clock Connection
77
Figure 7.5. Two Quads Clock Connection
77
Table 7.4. Quad Clock
77
Clock Frequency
78
Figure 7.6. Single Quad Clock Connection
78
Table 7.5. Recommend Settings for some Protocols
78
Application Case
79
Figure 7.7. Case I-A Clock Structure
79
Figure 7.8. Case I-B Clock Structure
79
Figure 7.9. Case II-A Clock Structure
80
Figure 7.10. Case II-B Clock Structure
80
Figure 7.11. Case II-C Clock Structure
80
Figure 7.12. Case III-A Clock Structure
81
Figure 7.13. Case IV-A Clock Structure
82
Figure 7.14. Case IV-B Clock Structure
83
Figure 7.15. 64B/66B PCS with Using GPLL
84
Figure 7.16. 64B/66B PCS Without Using GPLL (Case I)
84
PMA Clock Divider
85
Serdes/Pcs Reset
85
Figure 7.17. 64B/66B PCS Without Using GPLL (Case II)
85
Table 7.6. Reset and Power Control Signals
85
Figure 7.18. MPCS Mode Reset Sequence (Tx Path)
87
Figure 7.19. MPCS Mode Reset Sequence (Rx Path)
87
Figure 7.20. EPCS Mode Reset Sequence (Tx Path)
88
Figure 7.21. EPCS Mode Reset Sequence (Rx Path)
88
Serdes Equalization
89
Figure 8.1. Signal Distortion for Typical Backplane Application
89
Figure 8.2. Typical Backplane Application with Tx Equalizer
89
Figure 8.3. Typical Backplane Application with Rx Equalizer
90
Figure 8.4. Transmit Equalizer Block Diagram
90
Table 8.1. Description of Tx Voltage Levels
90
Tx Equalization
90
Figure 8.5. Definition of Tx Voltage Levels
91
Table 8.2. Pcie Tx Preset Ratios and Corresponding Coefficient Values
91
Figure 8.6. Receive Equalizer Block Diagram
92
Rx Equalization
92
Serdes/Pcs Debug Capabilities
93
Loopback Mode
93
Figure 9.1. PMA Loopback Mode
93
Figure 9.2. 8B/10B PCS Near-End Parallel Loopback Mode
94
Figure 9.3. 8B/10B PCS Far-End Parallel Loopback Mode
94
Signal Detector
95
Figure 9.4. 64B/66B PCS Loopback Mode
95
Figure 9.5. Signal Detector
95
Loss of Lock
96
Figure 9.6. CDR PLL Locking Flow
96
Table 9.1. Loss of Signal Conditions
96
Table 9.2. Typical Duration Time for each Lock Step
96
ECO Editor
97
Eye Monitor
97
Serdes/Pcs Register Access
98
Register Access Bus
98
Figure 10.1. Burst Read Transaction
98
Figure 10.2. Back-To-Back Read and Write Transaction
98
Register Space
99
Figure 10.3. Back-To-Back Write and Read Transaction
99
Table 10.1. Access Type Definition
99
Protocol Mode
100
PCI Express Mode
100
Generic 8B/10B Mode
100
Table 11.1. PCI Express Recommend AC Capacitance
100
PMA Only Mode
101
Ethernet Mode
101
Table 11.2. Gige Configuration and IDLE Ordered Sets Definition
102
Table 11.3. XAUI IDLE Ordered Sets Definition
102
SLVS-EC Mode
103
Table 11.4. 64B/66B Blocks Formats
103
Table 11.5. SLVS-EC Baud Rate
103
Displayport Mode
104
Coaxpress Mode
104
Table 11.6. General Parameters of Receiver Characteristics for SLVS-EC
104
Table 11.7. Displayport Recommend AC Capacitance
104
Serdes/Pcs Block Latency
105
Table 12.1. Transmit/Receive Serdes/Pcs Latency
105
Other Design Considerations
106
Simulation of the Serdes/Pcs
106
PMA PLL Filter
106
Reference Clock Source Selection
107
Figure 13.1. Example Connection to Analog Power and Reference Pins
107
Table 13.1. Recommended External Reference Resistor for Serval Differential Impedance Applications
107
Table 13.2. PCSREFMUX Usage
107
Spread Spectrum Clocking Support
108
Unused Quad/Channel and Power Supply
108
Electrical Idle
109
Multiple Data Rate Support
109
Table 13.3. Serdes Power Pins Numbering
109
Table 13.4. Electrical Idle Related Signals
109
Serdes/Pcs Generation in Radiant Software
110
Configuration GUI
110
Figure 14.1. MPCS Configuration GUI
110
Table 14.1. Protocol Descriptions
110
Attribute Summary
111
Table 14.2. Attributes Summary
111
Table 14.3. Attributes Descriptions
115
Primitive
117
Table 14.4. Pin-To-Pin Connection
117
Appendix A. Configuration Registers
122
A.1. PMA Registers
122
A.1.1. Register Address
122
A.1.2. Register Description
122
Table A. 1. Register Address
122
Table A. 2. Control Register 0 [Reg00]
122
Table A. 3. Clock Count for Error Counter Decrement [Reg01]
123
Table A. 4. Error Counter Threshold - Rx Idle Detect Max Latency [Reg02]
123
Table A. 5. Rx Impedance Ratio [Reg03]
123
Table A. 6. Tx PLL F Settings and PCLK Ratio [Reg04]
123
Table A. 7. Tx PLL M & N Settings [Reg05]
124
Table A. 8. Rx PLL F Settings and PCLK Ratio [Reg06]
124
Table A. 9. Rx PLL M & N Settings [Reg07]
125
Table A. 10. 250Ns Timer Base Count [Reg08]
125
Table A. 11. Tx Impedance Ratio [Reg09]
125
Table A. 12. Tx Post-Cursor Ratio [Reg0A]
125
Table A. 13. Tx Pre-Cursor Ratio [Reg0B]
126
Table A. 14. Power down Feature [Reg0E]
126
Table A. 15. Tx Amplitude Ratio [Reg18]
127
Table A. 16. CDR PLL Frequency Comparator Maximum Difference [Reg21]
127
Table A. 17. CDR PLL Frequency Comparator Counter [Reg22]
127
Table A. 18. EI4 Mode Register [Reg23]
127
Table A. 19. PMA Controller Status [Reg30]
127
Table A. 20. PRBS Control Register [Reg64]
128
Table A. 21. PRBS Error Counter Register [Reg65]
129
Table A. 22. PHY Reset Override Register [Reg66]
129
Table A. 23. PHY Power Override Register [Reg67]
129
Table A. 24. Transmit PLL Current Charge Pump [Reg69]
129
Table A. 25. Receive PLL Current Charge Pump [Reg6A]
130
Table A. 26. PCS Loopback Control [Reg74]
130
Table A. 27. CDR PLL Manual Control [Reg79]
131
Table A. 28. PMA Status [Reg7F]
131
A.2. MPCS Registers
132
A.2.1. Register Address
132
Table A. 29. Update Settings Command Register [Reg80]
132
Table A. 30. Register Address
132
A.2.2. Register Description
134
Table A. 31. MPCS Data Path Selection [Reg00]
134
Table A. 32. Tx Path Control [Reg10]
135
Table A. 33. 8B/10B Encoder Control [Reg11]
135
Table A. 34. Rx Path Control [Reg20]
136
Table A. 35. MPCS Rx Path Status [Reg21]
136
Table A. 36. 8B/10B Decoder Control [Reg22]
137
Table A. 37. Word Alignment Control [Reg30]
137
Table A. 38. Primary Word Alignment Pattern Byte 0 [Reg31]
137
Table A. 39. Primary Word Alignment Pattern Byte 1 [Reg32]
138
Table A. 40. Primary Word Alignment Pattern MSB [Reg33]
138
Table A. 41. Secondary Word Alignment Pattern Byte 0 [Reg34]
138
Table A. 42. Secondary Word Alignment Pattern Byte 1 [Reg35]
138
Table A. 43. Secondary Word Alignment Pattern MSB [Reg36]
138
Table A. 44. Word Alignment Pattern Mask Code Byte 0 [Reg37]
138
Table A. 45. Word Alignment Pattern Mask Code Byte 1 [Reg38]
138
Table A. 46. Word Alignment Pattern Mask Code MSB [Reg39]
139
Table A. 47. Sync_Det FSM Configuration 0 [Reg3A]
139
Table A. 48. Sync_Det FSM Configuration 1 [Reg3B]
139
Table A. 49. Sync_Det FSM Configuration 2 [Reg3C]
139
Table A. 50. Sync_Det FSM Configuration 3 [Reg3D]
139
Table A. 51. Number of Bit Slipped During Word Alignment [Reg3E]
140
Table A. 52. Primary Sync_Det Pattern Byte 0 [Reg3F]
140
Table A. 53. Primary Sync_Det Pattern Byte 1 [Reg40]
140
Table A. 54. Primary Sync_Det Pattern Byte 2 [Reg41]
140
Table A. 55. Primary Sync_Det Pattern Byte 3 [Reg42]
140
Table A. 56. Primary Sync_Det Pattern Byte MSB [Reg43]
140
Table A. 57. Secondary Sync_Det Pattern Byte 0 [Reg44]
141
Table A. 58. Secondary Sync_Det Pattern Byte 1 [Reg45]
141
Table A. 59. Secondary Sync_Det Pattern Byte 2 [Reg46]
141
Table A. 60. Secondary Sync_Det Pattern Byte 3 [Reg47]
141
Table A. 61. Secondary Sync_Det Pattern Byte MSB [Reg48]
141
Table A. 62. Sync_Det Pattern Mask Code Byte 0 [Reg49]
141
Table A. 63. Sync_Det Pattern Mask Code Byte 1 [Reg4A]
141
Table A. 64. Sync_Det Pattern Mask Code Byte 2 [Reg4B]
141
Table A. 65. Sync_Det Pattern Mask Code Byte 3 [Reg4C]
141
Table A. 66. Sync_Det Pattern Mask Code MSB [Reg4D]
141
Table A. 67. Lane Alignment Control [Reg50]
142
Table A. 68. Maximum Lane-To-Lane Skew [Reg51]
142
Table A. 69. Primary Lane Alignment Pattern Byte 0 [Reg52]
142
Table A. 70. Primary Lane Alignment Pattern Byte 1 [Reg53]
142
Table A. 71. Primary Lane Alignment Pattern Byte 2 [Reg54]
142
Table A. 75. Secondary Lane Alignment Pattern Byte 1 [Reg58]
143
Table A. 76. Secondary Lane Alignment Pattern Byte 2 [Reg59]
143
Table A. 77. Secondary Lane Alignment Pattern Byte 3 [Reg5A]
143
Table A. 78. Secondary Lane Alignment Pattern Byte MSB [Reg5B]
143
Table A. 79. Lane Alignment Pattern Mask Code [Reg5C]
143
Table A. 72. Primary Lane Alignment Pattern Byte 3 [Reg55]
143
Table A. 73. Primary Lane Alignment Pattern Byte MSB [Reg56]
143
Table A. 74. Secondary Lane Alignment Pattern Byte 0 [Reg57]
143
Table A. 80. Clock Frequency Compensation Control [Reg60]
144
Table A. 81. SKIP Pattern Insertion/Deletion Control [Reg61]
144
Table A. 82. Elastic FIFO High Water Line [Reg62]
144
Table A. 83. Elastic FIFO Low Water Line [Reg63]
145
Table A. 84. Primary SKIP Pattern Byte 0 [Reg64]
145
Table A. 85. Primary SKIP Pattern Byte 1 [Reg65]
145
Table A. 86. Primary SKIP Pattern Byte 2 [Reg66]
145
Table A. 87. Primary SKIP Pattern Byte 3 [Reg67]
145
Table A. 88. Primary SKIP Pattern MSB [Reg68]
145
Table A. 89. Secondary SKIP Pattern Byte 0 [Reg69]
145
Table A. 90. Secondary SKIP Pattern Byte 1 [Reg6A]
145
Table A. 91. Secondary SKIP Pattern Byte 2 [Reg6B]
145
Table A. 92. Secondary SKIP Pattern Byte 3 [Reg6C]
145
Table A. 93. Secondary SKIP Pattern MSB [Reg6D]
146
Table A. 94. SKIP Pattern Mask Code [Reg6E]
146
Table A. 95. 64B/66B PCS Tx Path Control [Reg80]
146
Table A. 96. 64B/66B PCS Tx FIFO Almost Full Setting Control [Reg81]
146
Table A. 97. 64B/66B PCS Tx FIFO Almost Empty Setting Control [Reg82]
146
Table A. 98. 64B/66B PCS Rx Path Control [Reg83]
146
Table A. 99. 64B/66B PCS CTC High Water Line Control [Reg84]
147
Table A. 100. 64B/66B PCS CTC Low Water Line Control [Reg85]
147
Table A. 101. 64B/66B PCS Block Align Shift [Reg86]
147
Table A. 102. 10GBASE-R BER Counter [Reg90]
147
Table A. 103. 10GBASE-R Block Error Counter [Reg91]
148
Table A. 104. 10GBASE-R Test Pattern Seed a Byte 0 [Reg92]
148
Table A. 105. 10GBASE-R Test Pattern Seed a Byte 1 [Reg93]
148
Table A. 106. 10GBASE-R Test Pattern Seed a Byte 2 [Reg94]
148
Table A. 107. 10GBASE-R Test Pattern Seed a Byte 3 [Reg95]
148
Table A. 108. 10GBASE-R Test Pattern Seed a Byte 4 [Reg96]
148
Table A. 109. 10GBASE-R Test Pattern Seed a Byte 5 [Reg97]
148
Table A. 110. 10GBASE-R Test Pattern Seed a Byte 6 [Reg98]
148
Table A. 111. 10GBASE-R Test Pattern Seed a Byte 7 [Reg99]
149
Table A. 112. 10GBASE-R Test Pattern Seed B Byte 0 [Reg9A]
149
Table A. 113. 10GBASE-R Test Pattern Seed B Byte 1 [Reg9B]
149
Table A. 114. 10GBASE-R Test Pattern Seed B Byte 2 [Reg9C]
149
Table A. 115. 10GBASE-R Test Pattern Seed B Byte 3 [Reg9D]
149
Table A. 116. 10GBASE-R Test Pattern Seed B Byte 4 [Reg9E]
149
Table A. 117. 10GBASE-R Test Pattern Seed B Byte 5 [Reg9F]
149
Table A. 118. 10GBASE-R Test Pattern Seed B Byte 6 [Rega0]
149
Table A. 119. 10GBASE-R Test Pattern Seed B Byte 7 [Rega1]
149
Table A. 120. 10GBASE-R Test Pattern Control 0 [Rega2]
150
Table A. 121. 10GBASE-R Test Pattern Control 1 [Rega3]
150
Table A. 122. 10GBASE-R Test Pattern Error Counter Byte 0 [Rega4]
151
Table A. 123. 10GBASE-R Test Pattern Error Counter Byte 1 [Rega5]
151
Table A. 124. PMA Control [Regc6]
151
Table A. 125. PMA Control [Regc7]
151
Table A. 126. Loopback Mode Control [Rege0]
152
Table A. 127. MPCS bist Control 0 [Rege1]
152
Table A. 129. User Defined bist Constant 1 Byte_0 [Rege3]
153
Table A. 130. User Defined bist Constant 1 Byte_1 [Rege4]
153
Table A. 131. User Defined bist Constant 1 Msbyte [Rege5]
153
Table A. 128. MPCS bist Control 1 [Rege2]
153
Table A. 132. User Defined bist Constant 2 Byte_0 [Rege6]
154
Table A. 133. User Defined bist Constant 2 Byte_1 [Rege7]
154
Table A. 134. User Defined bist Constant 2 MSB [Rege8]
154
Table A. 135. bist Status 0 [Rege9]
154
Table A. 136. bist Status 1 [Regea]
154
Table B. 1. 8B/10B Data Symbol Codes
155
Appendix B. 8B/10B Symbol Coding
155
Table B. 2. 8B/10B Control Symbol Codes
160
Table C. 1. Recommended Parameters for Serdes PLL
161
Appendix C. Calculating Parameters for Serdes PLL
161
Table C. 2. Serial Protocol Applications
166
Appendix D. Using Reveal Serdes Debug Tool
167
References
168
Technical Support Assistance
169
Revision History
170
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