Lattice Semiconductor CertusPro-NX - Table A. 67. Lane Alignment Control [Reg50]; Table A. 68. Maximum Lane-To-Lane Skew [Reg51]; Table A. 69. Primary Lane Alignment Pattern Byte 0 [Reg52]; Table A. 70. Primary Lane Alignment Pattern Byte 1 [Reg53]

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
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Table A. 67. Lane Alignment Control [reg50]
Field
Name
Access
Width
Reset
Description
[7:5]
reserved
RSVD
6
—
—
[4]
sec_laptn_en
RW
1
1’b0
Secondary Lane Alignment. Specifies if the secondary lane
alignment pattern matching is enabled or disabled.
1’b1 – Pattern Matching is enabled.
1’b0 – Pattern Matching is disabled.
[3:2]
lalign_ptn_len
RW
2
2’b0
Lane Alignment Pattern Length. Specifies the lane
alignment pattern length in byte.
2’b1x – 4-byte.
2’b01 – 2-byte.
2’b00 – 1-byte.
[1]
lalign_10b
RW
1
1’b0
Lane Alignment Coding Mode. Specifies the Lane
Alignment coding scheme of the input data.
1’b1 – input data is in 10b code mode.
1’b0 – input data is in 8b code mode.
[0]
lalign_en
RW
1
1’b0
Lane Alignment Enable. Specifies the lane alignment is
enabled or disabled.
1’b1 – Lane Alignment is enabled.
1’b0 – Lane Alignment is disabled.
Table A. 68. Maximum Lane-to-lane Skew [reg51]
Field
Name
Access
Width
Reset
Description
[7:4]
reserved
RSVD
6
—
—
[3:0]
max_lskew
RW
4
4’h0
Maximum Lane-to-lane skew specified in byte. If the
number of lane is less or equal to 4, these bits should be
configured as expected maximum lane-to-lane skew + 1. If
the number of lane is more than 4, these bits should be
configured as the expected maximum lane-to-lane skew +
2.
4’d10 – 10-byte skew.
…
4’d2 – 2-byte skew.
4’d1 – 1-byte skew.
4’d0 – reserved.
Note: The maximum lane-to-lane skew that can be
handled by hardware is 10-byte. These bits must be
correctly configured, and hardware uses these bits
without any checking.
Table A. 69. Primary Lane Alignment Pattern Byte 0 [reg52]
Field
Name
Access
Width
Reset
Description
[7:0]
pri_laptn_byte0
RW
8
8’h7c
Primary Lane Alignment Pattern Byte 0.
Table A. 70. Primary Lane Alignment Pattern Byte 1 [reg53]
Field
Name
Access
Width
Reset
Description
[7:0]
pri_laptn_byte1
RW
8
8’h0
Primary Lane Alignment Pattern Byte 1.
Table A. 71. Primary Lane Alignment Pattern Byte 2 [reg54]
Field
Name
Access
Width
Reset
Description
[7:0]
pri_laptn_byte2
RW
8
8’h0
Primary Lane Alignment Pattern Byte 2.