Lattice Semiconductor CertusPro-NX Usage Guide

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
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Table 5.8. EPCS Interface
Port Name
I/O
Width
Description
Clock and Reset Signals
epcs_rx_usr_clk_i
In
NL
User interface Rx clock input.
epcs_tx_usr_clk_i
In
NL
User interface Tx clock input.
epcs_tx_pcs_rstn_i
In
NL
Active low signal used to reset the Tx path of MPCS module.
epcs_rx_pcs_rstn_i
In
NL
Active low signal used to reset the Rx path of MPCS module.
epcs_rx_clk_o
Out
NL
PCS Rx output clock.
epcs_tx_clk_o
Out
NL
PCS Tx output clock.
epcs_rstn_i
In
NL
Fundamental reset that triggers PCS auto calibration.
epcs_clkin_i
In
NL
This low speed clock drives all calibration logic inside PMA
Controller. Connecting this clock port to epcs_tx_out_clk_o is
recommended. The recommended frequency range is
100-300 MHz. This clock should be stable and continuous after
power on.
Tx/Rx FIFO Signals
epcs_txdata_i
In
80*NL
For the signal mapping of this port, refer to Table 5.12.
epcs_rxdata_o
Out
80*NL
For the signal mapping of this port, refer to Table 5.12.
PMA Control and Status Signals
epcs_pwrdn_i
In
2*NL
This signal is used to put the PMA in powerdown mode. This
signal has only three states. This signal is required to be clocked
on mpcs_clkin_i.
2’b11 – deep low-power state.
2’b10 – low-power state.
2’b00 – operational state.
epcs_txhiz_i
In
NL
This signal is used to load Electrical Idle III in the Tx driver of the
PMA macro.
epcs_rxidle_o
Out
NL
This port is used to signal the Electrical Idle condition detected
by the PMA control logic. This signal is driven by epcs_clkin_i.
epcs_rxerr_i
In
NL
This signal is used to report to PMA control logic where error
data is detected by the PCS logic. Asserting this signal leads CDR
PLL switch back to the process of frequency lock acquisition.
epcs_fomreq_i
In
NL
This signal is used to request the FOM evaluation.
epcs_fomack_o
Out
NL
This signal is used to handshake the FOM evaluation request in
EPCS mode. It is asserted for a single clock cycle by the PMA
Controller. This signal is synchronous to epcs_tx_out_clk_o.
epcs_fomrslt_o
Out
8*NL
This signal is the evaluated FOM result. This signal is
synchronous to epcs_tx_out_clk_o.
epcs_rate_i
In
2*NL
EPCS rates:
2’b10 – Rate2
2’b01 – Rate1
2’b00 – Rate0
epcs_speed_o
Out
2*NL
EPCS current speeds:
2’b10 – Rate2
2’b01 – Rate1
2’b00 – Rate0
epcs_txval_i
In
NL
PHY transmit valid. This signal is used to transmit valid data. If
deasserted, the PMA macro is put in Electrical Idle 1. It can be
used for protocol requiring Electrical Idle, SATA, and must also
be deasserted as long as epcs_ready_o is not asserted. This
signal is also required to be generated one clock cycle earlier
than those corresponding epcs_tx_data_i signals.
epcs_txval_i = 0 causes the PMA Tx driver to generate the
Electrical Idle condition after 22 tx_pcs_clk cycles. If

Lattice Semiconductor CertusPro-NX Specifications

General

Brand	Lattice Semiconductor
Model	CertusPro-NX
Category	Computer Hardware
Language	English