CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
66 © 2020-2021 Lattice Semiconductor FPGA-TN-02245-0.81
All rights reserved. CONFIDENTIAL
The PRD Generator is loaded with a seed or its inverse at the start of a block every 128 blocks. Either 64-bit zeros or the
64-bit encoding for two Local Fault ordered sets can be selected as the data pattern, depending on seed settings. The
sync header is fixed to the control sync header, 2’b10. Thus, the pseudo-random pattern is a series of blocks with the
control sync header and a pseudo-random payload. The characteristics of the pseudo-random pattern can be varied by
varying the seed values and data input.
The PRD Checker module checks the pseudo-random pattern and counts the mismatch error, which can be recorded in
10GBASE-R Test Pattern Error Counter registers.
64B/66B Encoder
The 64B/66B Encoder module encodes 64-bit XGMII data and 8-bit XGMII control into the 66-bit data block. This
module can be optionally bypassed for test purpose.
In force packet mode (tx_frcpkt is asserted), the 64-bit data and 2-bit control from user logic are sent to Tx Gear Box
directly. Both 64B/66B Encoder and Scrambler modules are bypassed.
64B/66B Decoder
The 64B/66B Decoder module reverses the 64B/66B Encoder process, which converts the 66-bit data block to 64-bit
XGMII data and 8-bit XGMII control. This module can be optionally bypassed for test purpose.
The decoder performs functions such as sending local faults to the Media Access Control (MAC)/Reconciliation Sublayer
(RS) under reset and substituting error codes when the 10GBASE-R PCS rules are violated.
Tx FIFO
The Tx FIFO module is implemented to adapt Tx path clock frequency and phase difference between 64B/66B PCS
channel and fabric. It serves in following two application cases:
Case I (with GPLL)
In this case, GPLL is required to generate a 156.25 MHz clock as the write clock of Tx FIFO. User logic can write 64-bit
XGMII data and 8-bit XGMII control to Tx FIFO continuously, and the tx_fifo_wr can be tied to high. User logic does not
need to monitor the FIFO status in this case. Refer to Figure 6.26 for the timing diagram of this case.
For more details about this clocking scheme of 64B/66B PCS path, refer to the 64B/66B PCS with GPLL section.
Figure 6.26. 64B/66B PCS Tx FIFO Write Operation Case I
Case II (without GPLL)
In this case, user logic takes the clock originated from PMA as the write clock of Tx FIFO. The FIFO status needs to be
monitored, considering that the frequency of write clock and read clock is the same but the bandwidth between the
write side and the read side is different. The read side should be adapted to the bandwidth of 64B/66B Encoder
module 64bit@161.1328125MHz, and the write side is 64bit@161.1328125MHz.
User logic can implement FIFO write control logic by monitoring the almost full status of Tx FIFO. Once the almost full
flag is asserted, writing FIFO should be stopped immediately. Alternatively, user logic can make a pause of writing for
one clock cycle in every 33 cycles without monitoring the almost full status of Tx FIFO. For more details about this
clocking scheme of this case, refer to the 64B/66B PCS without GPLL section.
In Figure 6.27, the tx_fifo_wr is controlled properly so that there is neither overflow nor underflow. The almost full and
almost empty flags can be reset by accessing 64B/66B PCS Tx FIFO Almost Full Setting register and 64B/66B PCS Tx
Almost Empty Setting register.
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