Lattice Semiconductor CertusPro-NX Usage Guide

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
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All rights reserved. CONFIDENTIAL
Using This Technical Note
This technical note provides a thorough description of the complete functionality of the embedded SerDes and
associated PCS logic, including the description of:
 Architecture of the CertusPro-NX SerDes/PCS module and interface
 SerDes/PCS function
 Clock and reset
 SerDes/PCS debug capabilities
 SerDes/PCS register access
 SerDes/PCS usage for different protocols
 SerDes/PCS block latency
 SerDes/PCS generation in Lattice Radiant software
 The status and control registers associated with the SerDes and PCS logic, which can be accessed via the Lattice
Memory Mapped Interface (LMMI)
The electrical and timing characteristics of the embedded SerDes and the package pinout information are provided in
CertusPro-NX Family Data Sheet (FPGA-DS-02086).
The Lattice Radiant design tools support all modes of PCS. Most modes are dedicated to applications for specific
industry standard data protocols listed in the Features section. Other modes are more general purpose in nature in
order to let you customize your own application settings. Radiant design tools allow you to define the mode for each
quad in your design. This technical note describes operation of the SerDes and PCS for all modes supported by Lattice
Radiant software.

Lattice Semiconductor CertusPro-NX Specifications

General

Brand	Lattice Semiconductor
Model	CertusPro-NX
Category	Computer Hardware
Language	English