Lattice Semiconductor CertusPro-NX - Table A. 111. 10 GBASE-R Test Pattern Seed a Byte 7 [Reg99]; Table A. 112. 10 GBASE-R Test Pattern Seed B Byte 0 [Reg9 A]; Table A. 113. 10 GBASE-R Test Pattern Seed B Byte 1 [Reg9 B]; Table A. 114. 10 GBASE-R Test Pattern Seed B Byte 2 [Reg9 C]

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
FPGA-TN-02245-0.81 © 2020-2021 Lattice Semiconductor 149
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Table A. 111. 10GBASE-R Test Pattern Seed A Byte 7 [reg99]
Field
Name
Access
Width
Reset
Description
[7:0]
prtp_seed_a[57:56]
RW
8
8’h0
This register defines byte 7 of 10GBASE-R PCS test pattern
seed A.
Table A. 112. 10GBASE-R Test Pattern Seed B Byte 0 [reg9a]
Field
Name
Access
Width
Reset
Description
[7:0]
prtp_seed_b[7:0]
RW
8
8’h0
This register defines byte 0 of 10GBASE-R PCS test pattern
seed B.
Table A. 113. 10GBASE-R Test Pattern Seed B Byte 1 [reg9b]
Field
Name
Access
Width
Reset
Description
[7:0]
prtp_seed_b[15:8]
RW
8
8’h0
This register defines byte 1 of 10GBASE-R PCS test pattern
seed B.
Table A. 114. 10GBASE-R Test Pattern Seed B Byte 2 [reg9c]
Field
Name
Access
Width
Reset
Description
[7:0]
prtp_seed_b[23:16]
RW
8
8’h0
This register defines byte 2 of 10GBASE-R PCS test pattern
seed B.
Table A. 115. 10GBASE-R Test Pattern Seed B Byte 3 [reg9d]
Field
Name
Access
Width
Reset
Description
[7:0]
prtp_seed_b[31:24]
RW
8
8’h0
This register defines byte 3 of 10GBASE-R PCS test pattern
seed B.
Table A. 116. 10GBASE-R Test Pattern Seed B Byte 4 [reg9e]
Field
Name
Access
Width
Reset
Description
[7:0]
prtp_seed_b[39:32]
RW
8
8’h0
This register defines byte 4 of 10GBASE-R PCS test pattern
seed B.
Table A. 117. 10GBASE-R Test Pattern Seed B Byte 5 [reg9f]
Field
Name
Access
Width
Reset
Description
[7:0]
prtp_seed_b[47:40]
RW
8
8’h0
This register defines byte 5 of 10GBASE-R PCS test pattern
seed B.
Table A. 118. 10GBASE-R Test Pattern Seed B Byte 6 [rega0]
Field
Name
Access
Width
Reset
Description
[7:0]
prtp_seed_b[55:48]
RW
8
8’h0
This register defines byte 6 of 10GBASE-R PCS test pattern
seed B.
Table A. 119. 10GBASE-R Test Pattern Seed B Byte 7 [rega1]
Field
Name
Access
Width
Reset
Description
[7:0]
prtp_seed_b[57:56]
RW
8
8’h0
This register defines byte 7 of 10GBASE-R PCS test pattern
seed B.