Lattice Semiconductor CertusPro-NX - Table A. 75. Secondary Lane Alignment Pattern Byte 1 [Reg58]; Table A. 76. Secondary Lane Alignment Pattern Byte 2 [Reg59]; Table A. 77. Secondary Lane Alignment Pattern Byte 3 [Reg5 A]; Table A. 78. Secondary Lane Alignment Pattern Byte MSB [Reg5 B]

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
FPGA-TN-02245-0.81 © 2020-2021 Lattice Semiconductor 143
All rights reserved. CONFIDENTIAL
Table A. 72. Primary Lane Alignment Pattern Byte 3 [reg55]
Field
Name
Access
Width
Reset
Description
[7:0]
pri_laptn_byte3
RW
8
8’h0
Primary Lane Alignment Pattern Byte 3.
Table A. 73. Primary Lane Alignment Pattern Byte MSB [reg56]
Field
Name
Access
Width
Reset
Description
[7:6]
pri_laptn_byte3[9:8]
RW
2
2’h0
Primary Lane Alignment Pattern MSB Register reflects the bits
9 to 8 of primary lane alignment pattern byte 3 to 0.
[5:4]
pri_laptn_byte2[9:8]
RW
2
2’h0
[3:2]
pri_laptn_byte1[9:8]
RW
2
2’h0
[1:0]
pri_laptn_byte0[9:8]
RW
2
2’h1
Table A. 74. Secondary Lane Alignment Pattern Byte 0 [reg57]
Field
Name
Access
Width
Reset
Description
[7:0]
sec_laptn_byte0
RW
8
8’h7c
Secondary Lane Alignment Pattern Byte 0.
Table A. 75. Secondary Lane Alignment Pattern Byte 1 [reg58]
Field
Name
Access
Width
Reset
Description
[7:0]
sec_laptn_byte1
RW
8
8’h0
Secondary Lane Alignment Pattern Byte 1.
Table A. 76. Secondary Lane Alignment Pattern Byte 2 [reg59]
Field
Name
Access
Width
Reset
Description
[7:0]
sec_laptn_byte2
RW
8
8’h0
Secondary Lane Alignment Pattern Byte 2.
Table A. 77. Secondary Lane Alignment Pattern Byte 3 [reg5a]
Field
Name
Access
Width
Reset
Description
[7:0]
sec_laptn_byte3
RW
8
8’h0
Secondary Lane Alignment Pattern Byte 3.
Table A. 78. Secondary Lane Alignment Pattern Byte MSB [reg5b]
Field
Name
Access
Width
Reset
Description
[7:6]
sec_laptn_byte3[9:8]
RW
2
2’h0
Secondary Lane Alignment Pattern MSB Register reflects
the bits 9 to 8 of secondary lane alignment pattern byte 3
to 0.
[5:4]
sec_laptn_byte2[9:8]
RW
2
2’h0
[3:2]
sec_laptn_byte1[9:8]
RW
2
2’h0
[1:0]
sec_laptn_byte0[9:8]
RW
2
2’h1
Table A. 79. Lane Alignment Pattern Mask Code [reg5c]
Field
Name
Access
Width
Reset
Description
[7:4]
reserved
RSVD
4
—
—
[3:0]
lalign_mask_code
RW
4
4’h0
Lane Alignment Pattern mask code, bit 3 for pattern byte
3 and bit 0 for pattern byte 0.
1’b1 – the corresponding byte of lane alignment
pattern is ignored during alignment pattern matching.
1’b0 – the corresponding byte of lane alignment
pattern is not ignored during alignment pattern
matching.