CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
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Figure 7.13. Case IV-a Clock Structure
Case IV-b: Use Elastic Buffer
As shown in Figure 7.14, the rx_pcs_clk0 and rx_pcs_clk1 are the recovered clock from corresponding channel PMA Rx
CDR. Rx FIFO modules are enabled to eliminate the clock phase difference between rx_usr_clk and each channel
internal clock (rx_out_clk0 and rx_out_clk1). The rx_out_clk0 is used to drive FPGA global clock tree, and a leaf node of
this clock tree returning to MPCS is used as the read clock of Rx FIFO.
The rx_lalign_clk from Quad Common module is used by all lanes to replace each channel rx_pcs_clk to drive the Rx
path. The Lane Aligner modules are enabled for Rx lane-to-lane Deskew and for eliminating the phase difference
between rx_pcs_clk and rx_lalign_clk.
Elastic Buffer module works as CTC FIFO to compensate the frequency difference between rx_pcs_clka and
tx_lalign_clk. The tx_lalign_clk is from Quad Common module, and originated from certain channel PMA Tx PLL.
This mode is mainly designed for applications like PCIe and Ethernet. The rx_pcs_clk is discontinuous in certain
scenario. Some protocols also specify this clock tolerance compensation feature, considering the rx_pcs_clk containing
too much noise.
Figure 7.14 shows the two-lane application. The clock structure of multiple-lane applications (more than two) is similar
to this two-lane application.
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