CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
FPGA-TN-02245-0.81 © 2020-2021 Lattice Semiconductor 51
All rights reserved. CONFIDENTIAL
6.4.1.1. Data Bus Description
The bit mapping and transfer order of 40-bit Transmitter/Receiver data bus is described as follows. The data flowing
over the data bus can be either 8b data or 10b data.
ï‚· 8b data: the 8-bit raw data before 8B/10B encoding or after 8B/10B decoding.
ï‚· 10b data: the 10-bit DC-balanced code before 8B/10B decoding or after 8B/10B encoding.
The MPCS uses either 1-byte or 2-byte width internal data path, depending on protocol data rate. Moreover, the
MPCS-Fabric interface width can be configured as 1-byte, 2-byte, or 4-byte mode. Check the Clock Frequency section
for more information about the relationship between data bus width and data rate.
ï‚· 1-byte mode: receive, transmit or process 1-byte data per clock cycle; in this mode, only bit[9:0] of the data bus
are used to carry valid data; other 30 bits are left unused.
ï‚· 2-byte mode: receive, transmit or process 2-byte data per clock cycle; only bit[19:0] are valid in this mode.
ï‚· 4-byte mode: receive, transmit or process 4-byte data per clock cycle; all 40 bits are used in this mode.
The data flowing to/from fabric can be in 1-byte, 2-byte or 4-byte mode, but data inside MPCS are only in 1-byte,
2-byte mode. There is 2:1 gearing logic in MPCS Tx path to convert 4-byte data flowing from fabric to 2-byte data for
MPCS internal processing. Similarly, a 1:2 gearing exists in Rx path to convert 2-byte data at high speed to 4-byte
before they flow to fabric.
The bit mapping of Tx path data bus is described in Table 6.2. The bit mapping of Rx path data bus is described in
Table 6.3. Transfer ordering represents the serial order of sending.
Table 6.2. Bit Mapping of Tx Data Bus