Lattice Semiconductor CertusPro-NX Usage Guide

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
FPGA-TN-02245-0.81 © 2020-2021 Lattice Semiconductor 99
All rights reserved. CONFIDENTIAL
Figure 10.3. Back-to-Back Write and Read Transaction
Register Space
Each SerDes/PCS channel has independent register space which includes following category of registers:
 Configuration registers
 Control registers
 Status registers
 Status registers with clear-on-read
All register bits in Appendix A. Configure Registers are shown with bit7 as the significant bit on the left. Table 10.1
shows the abbreviations that are used to indicate what type of register access for each is supported.
Table 10.1. Access Type Definition
Access Type
Behaviour on Read Access
Behaviour on Write Access
RO
Returns register value.
Ignores write access.
WO
Returns 0.
Updates register value.
RW
Returns register value.
Updates register value.
RW1C
Returns register value.
Writing 1’b1 on register bit clears the bit to 1’b0.
Writing 1’b0 on register bit is ignored.
W/A
Returns register value.
Writing 1’b1 to clear related bit.
Writing 1’b0 is ignored.
CR
Clear on a read.
Ignores write access.
RSVD
Returns 0.
Ignores write access.

Lattice Semiconductor CertusPro-NX Specifications

General

Brand	Lattice Semiconductor
Model	CertusPro-NX
Category	Computer Hardware
Language	English