Lattice Semiconductor CertusPro-NX - Table A. 36. 8 B;10 B Decoder Control [Reg22]; Table A. 37. Word Alignment Control [Reg30]; Table A. 38. Primary Word Alignment Pattern Byte 0 [Reg31]

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
FPGA-TN-02245-0.81 © 2020-2021 Lattice Semiconductor 137
All rights reserved. CONFIDENTIAL
Field
Name
Access
Width
Reset
Description
[0]
rfifo_byte_shift
RW
1
1’b0
Byte shift. Specifies the data shift caused by COMMA byte
alignment operation.
1’b1 – there is one byte data shift.
1’b0 – there is no byte shift.
Table A. 36. 8B/10B Decoder Control [reg22]
Field
Name
Access
Width
Reset
Description
[7:1]
reserved
RSVD
7
—
—
[0]
dec_8b10b interleave
RW
1
1’b0
8B/10B decoder interleaving mode control
1’b0 – disabled.
1’b1 – enabled.
Table A. 37. Word Alignment Control [reg30]
Field
Name
Access
Width
Reset
Description
[7:6]
reserved
RW
2
—
—
[5]
wa_dis
RW
1
1’b0
Word Alignment. Specifies the Word Alignment Module is
enabled or disabled.
1’b1 – Word Alignment Module is disabled and the
input data is bypassed.
1’b0 – Word Alignment Module is enabled.
[4]
align_2byte_dis
RW
1
1’b0
2-Byte Alignment Pattern. Specifies where the pattern
appears in the data bus.
1’b1 – the pattern can appear at either [9:0] or [19:10]
of the data bus.
1’b0 – in a 2-byte internal data bus width mode, always
put the LSByte of the word alignment pattern to [9:0] of
the data bus.
[3]
sec_waptn_dis
RW
1
1’b0
Pattern Matching Enable. Specifies whether the secondary
word alignment pattern matching is enabled or not.
1’b1 – Secondary Word Alignment Pattern Matching is
disabled.
1’b0 – Secondary Word Alignment Pattern Matching is
enabled.
[2]
wa_ptn_20b
RW
1
1’b0
Word Align Pattern Bit Width. Specifies the bit width that
is to be used for the word alignment pattern.
1’b1 – Word Alignment Pattern is 20-bit width.
1’b0 – Word Alignment Pattern is 10-bit width; only
[9:0] of the 20-bit pattern and mask code are used.
[1]
syncdet_fsm_dis
RW
1
1’b0
Sync_Det FSM. Specifies the “sync_det” FSM is to be used
or is to be disabled.
1’b1 – disable “sync_det” FSM.
1’b0 – enable “sync_det” FSM.
[0]
auto_wa_dis
RW
1
1’b0
Word Align Mode. Specifies the use of automatic word
alignment or use of manual word alignment.
1’b1 – use manual word alignment mode.
1’b0 – use automatic word alignment mode.
Table A. 38. Primary Word Alignment Pattern Byte 0 [reg31]
Field
Name
Access
Width
Reset
Description
[7:0]
pri_wa_ptn [7:0]
RW
8
8’h7C
Specifies the 20-bit primary word alignment pattern. In
10-bit width mode, only bits 9 to 0 are applied.