EasyManuals Logo

Lattice Semiconductor CertusPro-NX Usage Guide

Default Icon
171 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #151 background imageLoading...
Page #151 background image
CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
FPGA-TN-02245-0.81 © 2020-2021 Lattice Semiconductor 151
All rights reserved. CONFIDENTIAL
Field
Name
Access
Width
Reset
Description
1’b1 – Zeros data pattern.
1’b0 – LF data pattern.
Table A. 122. 10GBASE-R Test Pattern Error Counter Byte 0 [rega4]
Field
Name
Access
Width
Reset
Description
[7:0]
tp_error_cnt[7:0]
RO/CR
8
8’h0
10GBASE-R Test Pattern Error Counter Byte 0 register
reflects the counter containing the number of errors
received during a pattern test. These bits are reset to all
zeros when the test-pattern error counter is read or upon
execution of the PCS reset. These bits are held at all ones
in the case of overflow. This counter counts either block
errors or bit errors depending on the test mode.
Note: When accessing this counter, must read the low
address byte (this register) first, then read the high
address byte (next register).
Table A. 123. 10GBASE-R Test Pattern Error Counter Byte 1 [rega5]
Field
Name
Access
Width
Reset
Description
[7:0]
tp_error_cnt[15:8]
RO/RC
8
8’h0
10GBASE-R Test Pattern Error Counter Byte 1 register
reflects the counter containing the number of errors
received during a pattern test. These bits are reset to all
zeros when the test-pattern error counter is read or upon
execution of the PCS reset. These bits are held at all ones
in the case of overflow. This counter counts either block
errors or bit errors depending on the test mode.
Table A. 124. PMA Control [regc6]
Field
Name
Access
Width
Reset
Description
[7:3]
reserved
RSVD
5
—
—
[3]
pma_rxval
RO
1
1’b0
The value of pma_rxval signal.
[2]
pma_ready
RO
1
1’b0
The value of pma_ready signal.
[1]
pma_phyrdy
RO
1
1’b0
The value of pma_phyrdy signal.
Table A. 125. PMA Control [regc7]
Field
Name
Access
Width
Reset
Description
[7:4]
reserved
RSVD
4
—
—
[3]
pma_rstn_ovrd
RW
1
1’b0
1’b1 – use bit[2] of this register to override the PMA
control signal "epcs_rstn".
1’b0 – use "pma_rstn" to drive "epcs_rstn".
[2]
pma_rstn
RW
1
1’b0
If bit[3] of this register is set to "1", use this bit to override
the PMA control signal "epcs_rstn".
1’b1 – drive "epcs_rstn" high if "pma_rstn_ovrd" is set
to "1".
1’b0 – drive "epcs_rstn" low if "pma_rstn_ovrd" is set
to "1".
[1]
txval_ovrd
RW
1
1’b0
1’b1 – use bit[0] of this register to override the PMA
control signal "epcs_txval".
1’b0 – use "pma_txval" to drive "epcs_txval".
[0]
txval
RW
1
1’b0
If bit[1] of this register is set to "1", use this bit to override
the PMA control signal "epcs_txval".
1’b1 – drive "epcs_txval" high if "txval_ovrd" is set to

Table of Contents

Other manuals for Lattice Semiconductor CertusPro-NX

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the Lattice Semiconductor CertusPro-NX and is the answer not in the manual?

Lattice Semiconductor CertusPro-NX Specifications

General IconGeneral
BrandLattice Semiconductor
ModelCertusPro-NX
CategoryComputer Hardware
LanguageEnglish