Lattice Semiconductor CertusPro-NX Usage Guide

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
FPGA-TN-02245-0.81 © 2020-2021 Lattice Semiconductor 115
All rights reserved. CONFIDENTIAL
Attribute
Selectable Values
Default
Dependency on Other Attributes
“6_SKEW”, “7_SKEW”,
“8_SKEW”, “9_SKEW”,
“10_SKEW”,
Primary Lane Alignment
Pattern Byte 0 (HEX)
N/A
17C
Active if Lane Alignment ==
“ENABLED”
Primary Lane Alignment
Pattern Byte 1 (HEX)
N/A
17C
Active if Lane Alignment ==
“ENABLED”
Primary Lane Alignment
Pattern Byte 2 (HEX)
N/A
00
Active if Lane Alignment ==
“ENABLED”
Primary Lane Alignment
Pattern Byte 3 (HEX)
N/A
00
Active if Lane Alignment ==
“ENABLED”
Secondary Lane Alignment
“ENABLED”, “DISABLED”
“DISABLED”
Active if Lane Alignment ==
“ENABLED”
Lane Alignment Mask Code
0
Active if Lane Alignment ==
“ENABLED”
Near End Parallel Loopback
“ENABLED”, “DISABLED”
“DISABLED”
—
Far End Parallel Loopback
“ENABLED”, “DISABLED”
“DISABLED”
—
Table 14.3. Attributes Descriptions
Attribute
Description
General
Protocol
Specifies the selected protocol of the MPCS Module, uses MPCS mode.
Bypass PCS
If enabled, MPCS Module is in EPCS mode.
Override TX PCS Mode
Specifies the value of reg00. tx_src_ovrd.
Override RX PCS Mode
Specifies the value of reg00. rx_src_ovrd.
Number of Lanes
Specifies the number of lane the user can use.
Lane ID
Specifies the first channel of the PCS instance.
Group Name
Specifies the group name of the PCS instance. Aligned channels have the same group
name.
Mode
Specifies the selected mode, which can be “Rx_only”, “Tx_only” or “Rx_and_“Tx”.
Data Rate (Gbps)
Specifies the data rate of the selected Protocol in Gbps.
Rate0 (Gbps)
Specifies the assigned data rate for the dynamic changing.
Rate1 (Gbps)
Specifies the assigned data rate for the dynamic changing.
Rate2 (Gbps)
Specifies the assigned data rate for the dynamic changing.
Bus Width
Specifies the user bus width available for the selected Protocol.
Ref Clk Freq (MHz)
Specifies the reference clock frequency of the selected Data Rate.
Use internal REFCLK
Specifies the use of internal reference clock from PCSREFMUX.
RefClk Selection for Quad0
Lists the reference clocks available for users.
External IO Pad RefClk for Quad0
Lists the available IO Pad Reference Clocks.
Bifurcation Select
Refer to Table 5.4 for more information about this attribute.
PCS Setup
Scrambler
Specifies the value of reg80. src_64b66b_dis.
64b66b Encoder
Specifies the value of reg80. end_64b66b_dis.
64b66b RX FIFO Almost Full
Specifies the value of reg81. tx_fifo_af.
64b66b TX FIFO Almost Empty
Specifies the value of reg82. tx_fifo_ae.
Descrambler
Specifies the value of reg83. descr_64b66b_dis.
64b66b Decoder
Specifies the value of reg83. dec_64b66b_dis.
Clock Frequency Compensation
Specifies the value of reg83. ctc_64b66b_dis.
Block Aligner
Specifies the value of reg83. balign_64b66b_dis.

Lattice Semiconductor CertusPro-NX Specifications

General

Brand	Lattice Semiconductor
Model	CertusPro-NX
Category	Computer Hardware
Language	English