CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
FPGA-TN-02245-0.81 © 2020-2021 Lattice Semiconductor 19
All rights reserved. CONFIDENTIAL
Table 5.1 shows the maximum number of available SerDes/PCS channels for each CertusPro-NX device. Refer to
CertusPro-NX Family Data Sheet (FPGA-DS-02086) for more details on the actual number of channels varying from
package to package.
Table 5.1. Maximum Number of SerDes/PCS Channels per CertusPro-NX Device
SerDes/PCS Architecture
Each CertusPro-NX SerDes/PCS quad includes four PMA channels, one PCI Express PCS Quad, one MPCS Quad, and
related glue logic. Each PMA channel integrates CDR for Receiver and PLL for Transmitter. The PCI Express PCS is
designed only for PCI Express, while the Multi-Protocol PCS (MPCS) is designed for other protocols.
CertusPro-NX device also integrates one PCI Express Link Layer Quad, which contains one PCIe ×1 block and one PCIe
×4 block. The PCIe ×4 PCI Express Link Layer block can be configured as ×1, ×2 or ×4 mode. The PCI Express Link Layer
block, PCI Express PCS channels, and PMA channels constitute the complete PCI Express Hard IP block. Table 5.2 shows
the maximum number of available PCI Express blocks information for the CertusPro-NX device. Refer to CertusPro-NX
Family Data Sheet (FPGA-DS-02086) for more details on the actual number of channels varying from package to
package.
Table 5.2. Maximum Number of PCI Express Blocks per CertusPro-NX Device
PCI Express Link Layer ×1 Block
PCI Express Link Layer ×4 Block
Figure 5.2 shows CertusPro-NX device SerDes/PCS quad architecture. For protocols other than PCI Express, the PCI
Express PCS can be bypassed. You can implement MPCS and PMA for Ethernet SGMII, XAUI, QSGMII, XGMII, SLVS-EC,
CoaXpress, DP/eDP or Generic 8B/10B applications. The MPCS can also be bypassed so that the SerDes/PCS module
works in PMA-only mode.
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