CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
FPGA-TN-02245-0.81 © 2020-2021 Lattice Semiconductor 25
All rights reserved. CONFIDENTIAL
Multi-Protocol Design Consideration
Different combinations of protocols with a SerDes/PCS quad are permitted subject to certain conditions. One of the
most basic requirements for two or more protocols sharing the same SerDes/PCS quad is that these protocols must
have the same reference clock frequency. This restriction is due to these protocols share the same reference clock
source.
Table 5.6 lists the support of mixed protocols within a CertusPro-NX SerDes/PCS quad. The reference clock must be
without spread spectrum when PCI Express and other protocols share the same SerDes/PCS quad.
Table 5.6. CertusPro-NX Mixed Protocols within a Quad
SerDes/PCS Block Signal Interface
For PCI Express Hard IP mode, the LMMI interface, TLP interface, and UCFG interface are accessible (Figure 5.8).
Figure 5.8. PCI Express Hard IP Mode
For PIPE mode, the PIPE interface and LMMI interface are accessible (Figure 5.9).
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