Lattice Semiconductor CertusPro-NX Usage Guide

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
138 © 2020-2021 Lattice Semiconductor FPGA-TN-02245-0.81
All rights reserved. CONFIDENTIAL
Table A. 39. Primary Word Alignment Pattern Byte 1 [reg32]
Field
Name
Access
Width
Reset
Description
[7:0]
pri_wa_ptn [17:10]
RW
8
8’h0
Specifies the 20-bit primary word alignment pattern. In
10-bit width mode, only bits 9 to 0 are applied.
Table A. 40. Primary Word Alignment Pattern MSB [reg33]
Field
Name
Access
Width
Reset
Description
[7:4]
reserved
RSVD
4
—
—
[3:2]
pri_wa_ptn[19:18]
RW
2
2’h0
Specifies the 20-bit primary word alignment pattern. In
10-bit width mode, only bits 9 to 0 are applied.
[1:0]
pri_wa_ptn[9: 8]
RW
2
2’h1
Specifies the 20-bit primary word alignment pattern. In
10-bit width mode, only bits 9 to 0 are applied.
Table A. 41. Secondary Word Alignment Pattern Byte 0 [reg34]
Field
Name
Access
Width
Reset
Description
[7:0]
sec_wa_ptn [7:0]
RW
8
8’h83
Specifies the 20-bit secondary word alignment pattern. In
10-bit width mode, only bits 9 to 0 are applied.
Table A. 42. Secondary Word Alignment Pattern Byte 1 [reg35]
Field
Name
Access
Width
Reset
Description
[7:0]
sec_wa_ptn [17:10]
RW
8
8’h0
Specifies the 20-bit secondary word alignment pattern. In
10-bit width mode, only bits 9 to 0 are applied.
Table A. 43. Secondary Word Alignment Pattern MSB [reg36]
Field
Name
Access
Width
Reset
Description
[7:4]
reserved
RSVD
4
—
—
[3:2]
sec_wa_ptn[19:18]
RW
2
2’h0
Specifies the 20-bit secondary word alignment pattern. In
10-bit width mode, only bits 9 to 0 are applied.
[1:0]
sec_wa_ptn[9: 8]
RW
2
2’h2
Specifies the 20-bit secondary word alignment pattern. In
10-bit width mode, only bits 9 to 0 are applied.
Table A. 44. Word Alignment Pattern Mask Code Byte 0 [reg37]
Field
Name
Access
Width
Reset
Description
[7:0]
wa_mask_code [7:0]
RW
8
8’h0
Word Align Mask Mode. Specifies the 20-bit word
alignment pattern. In 10-bit width mode, only bits 9 to 0
are applied.
1’b1 – the corresponding bit of word alignment pattern
is ignored during alignment pattern matching.
1’b0 – the corresponding bit of word alignment pattern
is not ignored during alignment pattern matching.
Table A. 45. Word Alignment Pattern Mask Code Byte 1 [reg38]
Field
Name
Access
Width
Reset
Description
[7:0]
wa_mask_code
[17:10]
RW
8
8’h0
Word Align Mask Mode. Specifies the 20-bit word
alignment pattern. In 10-bit width mode, only bits 9 to 0
are applied.
1’b1 – the corresponding bit of word alignment pattern
is ignored during alignment pattern matching.
1’b0 – the corresponding bit of word alignment pattern

Lattice Semiconductor CertusPro-NX Specifications

General

Brand	Lattice Semiconductor
Model	CertusPro-NX
Category	Computer Hardware
Language	English