Lattice Semiconductor CertusPro-NX Usage Guide

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
144 © 2020-2021 Lattice Semiconductor FPGA-TN-02245-0.81
All rights reserved. CONFIDENTIAL
Table A. 80. Clock Frequency Compensation Control [reg60]
Field
Name
Access
Width
Reset
Description
[7:6]
reserved
RSVD
3
—
—
[5]
sec_skip_en
RW
1
1’b0
Enable Secondary Skip. Specifies the secondary skip
pattern is enabled or disabled.
1’b1 – Pattern Matching is enabled.
1’b0 – Pattern Matching is disabled.
[4:3]
skip_ptn_len
RW
2
2’b00
Skip Pattern Length. Specifies the skip pattern length in
bytes.
2’b1x – 4-byte.
2’b01 – 2-byte.
2’b00 – 1-byte.
[2]
clk_comp_10b
RW
1
1’b0
Clock Compensation Coding Mode. Specifies the clock
compensation coding scheme for the input data.
1’b1 – input data is in 10b code mode.
1’b0 – input data is in 8b code mode.
[1]
ctc_fifo_en
RW
1
1’b0
Clock Compensation FIFO. Specifies the Clock
Compensation FIFO is enabled or disabled.
1’b1 – Clock Compensation FIFO is enabled.
1’b0 – Clock Compensation FIFO is disabled.
[0]
clk_comp_en
RW
1
1’b0
Enable Clock Frequency Compensation. Specifies the clock
frequency compensation is enabled or disabled.
1’b1 – Clock Frequency Compensation is disabled.
1’b0 – Clock Frequency Compensation is enabled.
Note: The combination of “ctc_fifo_en” and “clk_comp_en” are listed below: {ctc_fifo_en, clk_comp_en}
 2’b0x – bypass the input date of this module.
 2’b10 – the module works as asynchronous FIFO without clock frequency compensation.
 2’b11 – the module performs clock frequency compensation function.
Table A. 81. SKIP Pattern Insertion/Deletion Control [reg61]
Field
Name
Access
Width
Reset
Description
[7]
reserved
RSVD
1
—
—
[6:2]
ctc_repeat_wait
RW
5
5’h0
Clock Correction Frequency Control. It defines the
minimum number of clock cycles between two clock
correction events, including SKIP deletion and insertion.
x(x=1 to 31) – The next time of SKIP deletion or
insertion must be x clock cycles away from the current
SKIP deletion or insertion.
1’b0 – on constraint on SKIP deletion and insertion.
[1:0]
min_ipg_cnt
RW
2
2’h0
Minimum SKIP pattern count. Used to guarantee the
minimum number of bytes between packets (that is the
minimum Inter Packet Gap) after SKIP deletion.
2’b11 – at least three SKIP pattern is kept in IPG.
2’b10 – at least two SKIP pattern is kept in IPG.
2’b01 – at least one SKIP pattern is kept in IPG.
2’b00 – no constraint on SKIP deletion.
Note: The length in byte of SKIP pattern is defined in “skp_ptn_len” domain register “Clock Frequency Compensation Control”.
Table A. 82. Elastic FIFO High Water Line [reg62]
Field
Name
Access
Width
Reset
Description
[7:5]
reserved
RSVD
3
—
—
[4:0]
high_water_line
RW
5
5’b10110
Specifies the Clock Compensation FIFO high water line.
Mean is 5’b10000.

Lattice Semiconductor CertusPro-NX Specifications

General

Brand	Lattice Semiconductor
Model	CertusPro-NX
Category	Computer Hardware
Language	English