Lattice Semiconductor CertusPro-NX Usage Guide

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
132 © 2020-2021 Lattice Semiconductor FPGA-TN-02245-0.81
All rights reserved. CONFIDENTIAL
Table A. 29. Update Settings Command Register [reg80]
Field
Name
Access
Width
Reset
Description
[7:1]
reserved
RSVD
7
7’h0
—
[0]
reg_apply
WO
1
1’b0
This bit is transient (read always report 0) where writing
1’b1 to this bit will trigger a new computation of PMA
settings based on values written into related PMA
registers.
A.2. MPCS Registers
A.2.1. Register Address
Table A. 30. Register Address
Offset LMMI
Register Name
Access Type
Description
8’h00
reg00
RW
MPCS Data Path Selection.
8’h10
reg10
RW
MPCS Tx Path Control.
8’h11
reg11
RW
8B/10B Encoder Control.
8’h20
reg20
RW
MPCS Rx Path Control.
8’h21
reg21
RW
MPCS Rx Path Status.
8’h22
reg22
RW
8B/10B Decoder Control.
8’h30
reg30
RW
Word Alignment Control.
8’h31
reg31
RW
Primary Word Alignment Pattern Byte 0.
8’h32
reg32
RW
Primary Word Alignment Pattern Byte 1.
8’h33
reg33
RW
Primary Word Alignment Pattern MSB.
8’h34
reg34
RW
Secondary Word Alignment Pattern Byte 0.
8’h35
reg35
RW
Secondary Word Alignment Patter Byte 1.
8’h36
reg36
RW
Secondary Word Alignment Pattern MSB.
8’h37
reg37
RW
Word Alignment Pattern Mask Code Byte 0.
8’h38
reg38
RW
Word Alignment Pattern Mask Code Byte 1.
8’h39
reg39
RW
Word Alignment Pattern Mask Code MSB.
8’h3a
reg3a
RW
Sync_Det FSM Configuration 0.
8’h3b
reg3b
RW
Sync_Det FSM Configuration 1.
8’h3c
reg3c
RW
Sync_Det FSM Configuration 2.
8’h3d
reg3d
RW
Sync_Det FSM Configuration 3.
8’h3e
reg3e
RO
Number of Bit Slipped During Word Alignment.
8’h3f
reg3f
RW
Primary Sync_Det Pattern Byte 0.
8’h40
reg40
RW
Primary Sync_Det Pattern Byte 1.
8’h41
reg41
RW
Primary Sync_Det Pattern Byte 2.
8’h42
reg42
RW
Primary Sync_Det Pattern Byte 3.
8’h43
reg43
RW
Primary Sync_Det Pattern MSB.
8’h44
reg44
RW
Secondary Sync_Det Pattern Byte 0.
8’h45
reg45
RW
Secondary Sync_Det Pattern Byte 1.
8’h46
reg46
RW
Secondary Sync_Det Pattern Byte 2.
8’h47
reg47
RW
Secondary Sync_Det Pattern Byte 3.
8’h48
reg48
RW
Secondary Sync_Det Pattern MSB.
8’h49
reg49
RW
Sync_Det Pattern Mask Code Byte 0.
8’h4a
reg4a
RW
Sync_Det Pattern Mask Code Byte 1.
8’h4b
reg4b
RW
Sync_Det Pattern Mask Code Byte 2.
8’h4c
reg4c
RW
Sync_Det Pattern Mask Code Byte 3.

Lattice Semiconductor CertusPro-NX Specifications

General

Brand	Lattice Semiconductor
Model	CertusPro-NX
Category	Computer Hardware
Language	English