Lattice Semiconductor CertusPro-NX - Figure 6.31. Quad Reference Clock Source

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
FPGA-TN-02245-0.81 © 2020-2021 Lattice Semiconductor 71
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Figure 6.31. Quad Reference Clock Source
Both SDQx_REFCLKP/N receive buffer and SD_EXTx_REFCLKP/N receive buffer can convert differential input to
single-ended output to drive the clock tree. However, the detailed implementation of these two receive buffer are
different.
The SDQx_REFCLKP/N receive buffer is unterminated input and must be DC coupled out of chip. This SDQx_REFCLKP/N
receive buffer supports voltage signal input or current signal, such as High Speed Current Steering Logic (HCSL). The
SD_EXTx_REFCLKP/N receive buffer supports both voltage signal input and current signal input, such as LVDS, HCSL.
SD_EXTx_REFCLKP/N receive buffer can also be AC coupled out of chip. However, it is recommended to use LVDS
source to drive SD_EXTx_REFCLKP/N receive buffer.
For electrical and timing characteristics of SDQx_REFCLKP/N receive buffer and SD_EXTx_REFCLKP/N receive buffer,
check CertusPro-NX Family Data Sheet (FPGA-DS-02086).