CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
FPGA-TN-02245-0.81 © 2020-2021 Lattice Semiconductor 15
All rights reserved. CONFIDENTIAL
Features
ï‚· Single Channel MPCS Functionalities
From 625 Mb/s up to 10.3125 Gb/s per channel
Word alignment and link synchronization FSM
Supports DisplayPort, SLVS-EC, CoaXPress, and Ethernet 1000BASE-X/SGMII/XAUI/QSGMII protocols
Supports popular 8B/10B PCS-based protocols
Supports user-specified generic 8B/10B mode
Supports Ethernet 64B/66B coding and decoding
Supports per channel configuration
PMA-only mode allows direct 8-bit or 10-bit interface to FPGA logic
ï‚· Multiple Channel Alignment
Up to eight channels of the same protocol
Minimized Transmitter (Tx) lane-to-lane skew
Receiver (Rx) multiple lane de-skew (up to 100UI)
ï‚· Multiple Protocol Clock Tolerance Compensation (CTC) logic
Compensates for frequency difference between reference clock and received data rate
Allows user-defined SKIP pattern of 1, 2, or 4 bytes in length
ï‚· Integrated Loopback Modes for System Debugging
Two loopback modes are provided by SerDes (PMA)
Two loopback modes are provided by MPCS 8B/10B mode
Three loopback modes are provided by MPCS 64B/66B mode
ï‚· Rx Eye Monitor
Integrated 2D eye-scan for each Rx channel
First on-chip SerDes debug tool in Lattice general purpose FPGAs
ï‚· SerDes Power Supply Monitor
Integrated real-time monitor for SerDes power supply
ï‚· Easy-to-Use Design Interface in Lattice Radiant
TM
Design Tool
Easy-to-use Graphic User Interface (GUI)
Some easy-to-use soft IP cores and example projects available
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