CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
FPGA-TN-02245-0.81 © 2020-2021 Lattice Semiconductor 161
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Appendix C. Calculating Parameters for SerDes PLL
Table C. 1 lists the recommended parameters for SerDes PLL in specific data rate. For detailed information about PLL
clock setting, refer to PLL Clock Setting section. N need be set as 5, 10 or 20, when 8B/10B PCS is required.
Table C. 1. Recommended Parameters for SerDes PLL