Lattice Semiconductor CertusPro-NX Usage Guide

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
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Word
Aligner
8B/10B
Decoder
Elastic
Buffer
Rx
PMA
Lane
Aligner
RX Path
Rx FIFO
/2,
/1
DFF
DFF
Clock
Tree
DFF
Fabric
rx_pcs_clk
rx_lalign_clk
rx_pcs_clka
tx_pcs_clk
tx_lalign_clk
rx_pcs_clkb
rx_out_clk
rx_usr_clk
Figure 7.9. Case II-a Clock Structure
Case II-b: Bypass Rx FIFO
As shown in Figure 7.10, in this case, the Rx FIFO module is bypassed to achieve low latency or deterministic latency. A
synchronous DFF is used to capture the input data instead of Rx FIFO. The rx_out_clk drives FPGA global clock tree, and
a leaf node of this clock tree returning to MPCS is used to drive user logic.
What should be noted is that the critical timing constraint must be applied to Fabric-MPCS interface, considering the
phase difference between rx_out_clk and rx_usr_clk. The Tx FIFO must be enabled, if the timing analysis results show
that the timing constraint cannot be met.
Word
Aligner
10B/8B
Decoder
Elastic
Buffer
Rx
PMA
Lane
Aligner
rx_pcs_clk
RX Path
RX FIFO
/2,
/1
DFF
DFF
Clock
Tree
DFF
Fabric
DFF
rx_pcs_clka
rx_lalign_clk
tx_pcs_clk
tx_lalign_clk rx_pcs_clkb
rx_out_clk
rx_usr_clk
Figure 7.10. Case II-b Clock Structure
Case II-c: Use Elastic Buffer
As shown in Figure 7.11, the rx_pcs_clk is the recovered clock from PMA Rx CDR, the tx_pcs_clk is the generated clock
from PMA Tx PLL. The rx_out_clk is used to drive FPGA global clock tree, and the rx_usr_clk is a leaf node of this clock
tree returning to MPCS. Rx FIFO module works as asynchronous FIFO to eliminate the phase difference between
rx_out_clk and rx_usr_clk.
Lane Aligner module is bypassed, considering this a single lane application. The Elastic Buffer module works as CTC
FIFO, to compensate the frequency difference between rx_pcs_clk and tx_pcs_clk.
This mode is mainly designed for applications like PCIe and Ethernet, the rx_pcs_clk is discontinuous in certain scenario.
Some protocols also specifies this clock tolerance compensation feature, as the rx_pcs_clk may contain too much noise.
Word
Aligner
10B/8B
Decoder
Elastic Buffer
Rx
PMA
Lane
Aligner
RX Path
Rx FIFO
/2,
/1
DFF
Clock
Tree
DFF
Fabric
rx_pcs_clk
rx_lalign_clk
rx_pcs_clka
tx_pcs_clk
tx_lalign_clk
rx_pcs_clkb
rx_out_clk
rx_usr_clk
Figure 7.11. Case II-c Clock Structure

Lattice Semiconductor CertusPro-NX Specifications

General

Brand	Lattice Semiconductor
Model	CertusPro-NX
Category	Computer Hardware
Language	English