Lattice Semiconductor CertusPro-NX Usage Guide

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
FPGA-TN-02245-0.81 © 2020-2021 Lattice Semiconductor 147
All rights reserved. CONFIDENTIAL
Field
Name
Access
Width
Reset
Description
1’b0 – Only delete one sequence ordered set each time
when doing clock frequency compensation.
[4]
pcs_64b66b_nofpll
RW
1
1’b0
1’b1 – No GPLL is used to generate user clock.
1’b0 – GPLL is used to generate user clock.
[3]
balign_64b66b_dis
RW
1
1’b0
Enable 64B/66B Block Aligner. Specifies the 64B/66B block
aligner is enabled or disabled.
1’b1 – 64B/66B block aligner is disabled.
1’b0 – 64B/66B block aligner is enabled.
[2]
ctc_64b66b_dis
RW
1
1’b0
Enable 64B/66B CTC. Specifies the 64B/66B Clock
Frequency Compensation is enabled or disabled.
1’b1 – 64B/66B Clock Frequency Compensation is
disabled.
1’b0 – 64B/66B Clock Frequency Compensation is
enabled.
[1]
dec_64b66b_dis
RW
1
1’b0
Enable 64B/66B Decoder. Specifies the 64B/66B Decoder
is enabled or disabled.
1’b1 – 64B/66B Decoder is disabled.
1’b0 – 64B/66B Decoder is enabled.
[0]
descr_64b66b_dis
RW
1
1’b0
Enable 64B/66B Descrambler. Specifies the 64B/66B
Descrambler is enabled or disabled.
1’b1 – 64B/66B Descrambler is disabled.
1’b0 – 64B/66B Descrambler is enabled.
Table A. 99. 64B/66B PCS CTC High Water Line Control [reg84]
Field
Name
Access
Width
Reset
Description
[7:5]
reserved
RSVD
3
—
—
[4:0]
ctc_64b66b_high
RW
5
5’h0C
64B/66B PCS CTC High water line reflects the high water
line of clock frequency compensation.
Table A. 100. 64B/66B PCS CTC Low Water Line Control [reg85]
Field
Name
Access
Width
Reset
Description
[7:5]
reserved
RSVD
3
—
—
[4:0]
ctc_64b66b_low
RW
5
5’h4
64B/66B PCS CTC Low water line reflects the low water
line of clock frequency compensation.
Table A. 101. 64B/66B PCS Block Align Shift [reg86]
Field
Name
Access
Width
Reset
Description
[7]
reserved
RSVD
1
—
—
[6:0]
balign_64b66b_shift
RO
7
7’h0
64B/66B PCS Block Align Shift register reflects the bit
shifting of block alignment.
Table A. 102. 10GBASE-R BER Counter [reg90]
Field
Name
Access
Width
Reset
Description
[7:6]
reserved
RSVD
1
—
—
[5:0]
ber_count
RO/CR
6
6’h0
10GBASE-R BER Counter register reflects the BER counter
is a six-bit-count as defined by the ber_count variable in
49.2.14.2 for 10GBASE-R. These bits are the reset to all
zeros when the register is read or upon execution of the
PCS reset. These bits are to be held at all ones in the case
of overflow.

Lattice Semiconductor CertusPro-NX Specifications

General

Brand	Lattice Semiconductor
Model	CertusPro-NX
Category	Computer Hardware
Language	English