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Lattice Semiconductor CertusPro-NX - Introduction

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CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
14 © 2020-2021 Lattice Semiconductor FPGA-TN-02245-0.81
All rights reserved. CONFIDENTIAL
Introduction
The Lattice Semiconductor CertusPro-NX device family has up to 8 channels embedded SerDes with associated Physical
Coding Sublayer (PCS) logic, which supports PCI Express Gen1/2/3 hard IP Core, DisplayPort, 10GBASE-R, 1000BASE-X,
SGMII, QSGMII, XAUI, SLVS-EC, and CoaXPress protocols. There are two kinds of Physical Coding Sublayer logic inside
the CertusPro-NX device: one is for PCI Express only, the other is Multi-Protocol Physical Coding Sublayer (MPCS) for
protocols other than PCI Express.
Each channel of MPCS contains dedicated transmit and receive logic for high-speed, full-duplex serial data transfer at
data rates up to 10.3125 Gb/s. The MPCS logic in each channel can be configured to support corresponding protocols.
In addition, the protocol-based logic can be fully or partially bypassed in a number of configurations to provide you the
flexibility of designing your own high-speed data interface. SerDes channel input can be independently AC-coupled or
DC-coupled to meet the requirements from different protocols.

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