Lattice Semiconductor CertusPro-NX - Architecture Overview; Device Architecture; Figure 5.1. Certuspro-NX 100 K Device Block Diagram

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CertusPro-NX SerDes/PCS Usage Guide

Preliminary Technical Note

Architecture Overview

Device Architecture

The SerDes/PCS block is arranged in quads containing logic for four full-duplex data channels. Figure 5.1 shows the

arrangement of SerDes/PCS Quads on the CertusPro-NX 100k device.

PLL

SERDES/PCS X4

OSC

Configuration

& Security

I/O Bank (Bank 0)

Large

RAM

ALU

ADC

(2Ch)

Large

RAM

I/O Bank

(Bank 1)

I/O Bank

(Bank 2)

I/O Bank (Bank 5) I/O Bank (Bank 4) I/O Bank (Bank 3) PLL

I/O Bank

(Bank 7)

I/O Bank

(Bank 6)

PLL

CDR

(2Ch)

PLL

Large

RAM

Large

RAM

SERDES/PCS X4

Large

RAM

Large

RAM

Large

RAM

PCIe LL(X4+X1)

Figure 5.1. CertusPro-NX 100k Device Block Diagram

Main Page

Table of Contents3
Glossary11
- Introduction14
- Features15
- Using this Technical Note16
- Standards Supported17
- Table 4.1. Standards Supported by the Serdes/Pcs17
- Architecture Overview18
- Serdes/Pcs Function Description47
- Clocks and Reset72
- Serdes Equalization89
- Serdes/Pcs Debug Capabilities93
Appendix A. Configuration Registers122
- A.1. PMA Registers122
- A.1.1. Register Address122
- A.1.2. Register Description122
Table A. 1. Register Address122
Table A. 2. Control Register 0 [Reg00]122
Table A. 3. Clock Count for Error Counter Decrement [Reg01]123
Table A. 4. Error Counter Threshold - Rx Idle Detect Max Latency [Reg02]123
Table A. 5. Rx Impedance Ratio [Reg03]123
Table A. 6. Tx PLL F Settings and PCLK Ratio [Reg04]123
Table A. 7. Tx PLL M & N Settings [Reg05]124
Table A. 8. Rx PLL F Settings and PCLK Ratio [Reg06]124
Table A. 9. Rx PLL M & N Settings [Reg07]125
Table A. 10. 250Ns Timer Base Count [Reg08]125
Table A. 11. Tx Impedance Ratio [Reg09]125
Table A. 12. Tx Post-Cursor Ratio [Reg0A]125
Table A. 13. Tx Pre-Cursor Ratio [Reg0B]126
Table A. 14. Power down Feature [Reg0E]126
Table A. 15. Tx Amplitude Ratio [Reg18]127
Table A. 16. CDR PLL Frequency Comparator Maximum Difference [Reg21]127
Table A. 17. CDR PLL Frequency Comparator Counter [Reg22]127
Table A. 18. EI4 Mode Register [Reg23]127
Table A. 19. PMA Controller Status [Reg30]127
Table A. 20. PRBS Control Register [Reg64]128
Table A. 21. PRBS Error Counter Register [Reg65]129
Table A. 22. PHY Reset Override Register [Reg66]129
Table A. 23. PHY Power Override Register [Reg67]129
Table A. 24. Transmit PLL Current Charge Pump [Reg69]129
Table A. 25. Receive PLL Current Charge Pump [Reg6A]130
Table A. 26. PCS Loopback Control [Reg74]130
Table A. 27. CDR PLL Manual Control [Reg79]131
Table A. 28. PMA Status [Reg7F]131
- A.2. MPCS Registers132
- A.2.1. Register Address132
Table A. 29. Update Settings Command Register [Reg80]132
Table A. 30. Register Address132
- A.2.2. Register Description134
Table A. 31. MPCS Data Path Selection [Reg00]134
Table A. 32. Tx Path Control [Reg10]135
Table A. 33. 8B/10B Encoder Control [Reg11]135
Table A. 34. Rx Path Control [Reg20]136
Table A. 35. MPCS Rx Path Status [Reg21]136
Table A. 36. 8B/10B Decoder Control [Reg22]137
Table A. 37. Word Alignment Control [Reg30]137
Table A. 38. Primary Word Alignment Pattern Byte 0 [Reg31]137
Table A. 39. Primary Word Alignment Pattern Byte 1 [Reg32]138
Table A. 40. Primary Word Alignment Pattern MSB [Reg33]138
Table A. 41. Secondary Word Alignment Pattern Byte 0 [Reg34]138
Table A. 42. Secondary Word Alignment Pattern Byte 1 [Reg35]138
Table A. 43. Secondary Word Alignment Pattern MSB [Reg36]138
Table A. 44. Word Alignment Pattern Mask Code Byte 0 [Reg37]138
Table A. 45. Word Alignment Pattern Mask Code Byte 1 [Reg38]138
Table A. 46. Word Alignment Pattern Mask Code MSB [Reg39]139
Table A. 47. Sync_Det FSM Configuration 0 [Reg3A]139
Table A. 48. Sync_Det FSM Configuration 1 [Reg3B]139
Table A. 49. Sync_Det FSM Configuration 2 [Reg3C]139
Table A. 50. Sync_Det FSM Configuration 3 [Reg3D]139
Table A. 51. Number of Bit Slipped During Word Alignment [Reg3E]140
Table A. 52. Primary Sync_Det Pattern Byte 0 [Reg3F]140
Table A. 53. Primary Sync_Det Pattern Byte 1 [Reg40]140
Table A. 54. Primary Sync_Det Pattern Byte 2 [Reg41]140
Table A. 55. Primary Sync_Det Pattern Byte 3 [Reg42]140
Table A. 56. Primary Sync_Det Pattern Byte MSB [Reg43]140
Table A. 57. Secondary Sync_Det Pattern Byte 0 [Reg44]141
Table A. 58. Secondary Sync_Det Pattern Byte 1 [Reg45]141
Table A. 59. Secondary Sync_Det Pattern Byte 2 [Reg46]141
Table A. 60. Secondary Sync_Det Pattern Byte 3 [Reg47]141
Table A. 61. Secondary Sync_Det Pattern Byte MSB [Reg48]141
Table A. 62. Sync_Det Pattern Mask Code Byte 0 [Reg49]141
Table A. 63. Sync_Det Pattern Mask Code Byte 1 [Reg4A]141
Table A. 64. Sync_Det Pattern Mask Code Byte 2 [Reg4B]141
Table A. 65. Sync_Det Pattern Mask Code Byte 3 [Reg4C]141
Table A. 66. Sync_Det Pattern Mask Code MSB [Reg4D]141
Table A. 67. Lane Alignment Control [Reg50]142
Table A. 68. Maximum Lane-To-Lane Skew [Reg51]142
Table A. 69. Primary Lane Alignment Pattern Byte 0 [Reg52]142
Table A. 70. Primary Lane Alignment Pattern Byte 1 [Reg53]142
Table A. 71. Primary Lane Alignment Pattern Byte 2 [Reg54]142
Table A. 75. Secondary Lane Alignment Pattern Byte 1 [Reg58]143
Table A. 76. Secondary Lane Alignment Pattern Byte 2 [Reg59]143
Table A. 77. Secondary Lane Alignment Pattern Byte 3 [Reg5A]143
Table A. 78. Secondary Lane Alignment Pattern Byte MSB [Reg5B]143
Table A. 79. Lane Alignment Pattern Mask Code [Reg5C]143
Table A. 72. Primary Lane Alignment Pattern Byte 3 [Reg55]143
Table A. 73. Primary Lane Alignment Pattern Byte MSB [Reg56]143
Table A. 74. Secondary Lane Alignment Pattern Byte 0 [Reg57]143
Table A. 80. Clock Frequency Compensation Control [Reg60]144
Table A. 81. SKIP Pattern Insertion/Deletion Control [Reg61]144
Table A. 82. Elastic FIFO High Water Line [Reg62]144
Table A. 83. Elastic FIFO Low Water Line [Reg63]145
Table A. 84. Primary SKIP Pattern Byte 0 [Reg64]145
Table A. 85. Primary SKIP Pattern Byte 1 [Reg65]145
Table A. 86. Primary SKIP Pattern Byte 2 [Reg66]145
Table A. 87. Primary SKIP Pattern Byte 3 [Reg67]145
Table A. 88. Primary SKIP Pattern MSB [Reg68]145
Table A. 89. Secondary SKIP Pattern Byte 0 [Reg69]145
Table A. 90. Secondary SKIP Pattern Byte 1 [Reg6A]145
Table A. 91. Secondary SKIP Pattern Byte 2 [Reg6B]145
Table A. 92. Secondary SKIP Pattern Byte 3 [Reg6C]145
Table A. 93. Secondary SKIP Pattern MSB [Reg6D]146
Table A. 94. SKIP Pattern Mask Code [Reg6E]146
Table A. 95. 64B/66B PCS Tx Path Control [Reg80]146
Table A. 96. 64B/66B PCS Tx FIFO Almost Full Setting Control [Reg81]146
Table A. 97. 64B/66B PCS Tx FIFO Almost Empty Setting Control [Reg82]146
Table A. 98. 64B/66B PCS Rx Path Control [Reg83]146
Table A. 99. 64B/66B PCS CTC High Water Line Control [Reg84]147
Table A. 100. 64B/66B PCS CTC Low Water Line Control [Reg85]147
Table A. 101. 64B/66B PCS Block Align Shift [Reg86]147
Table A. 102. 10GBASE-R BER Counter [Reg90]147
Table A. 103. 10GBASE-R Block Error Counter [Reg91]148
Table A. 104. 10GBASE-R Test Pattern Seed a Byte 0 [Reg92]148
Table A. 105. 10GBASE-R Test Pattern Seed a Byte 1 [Reg93]148
Table A. 106. 10GBASE-R Test Pattern Seed a Byte 2 [Reg94]148
Table A. 107. 10GBASE-R Test Pattern Seed a Byte 3 [Reg95]148
Table A. 108. 10GBASE-R Test Pattern Seed a Byte 4 [Reg96]148
Table A. 109. 10GBASE-R Test Pattern Seed a Byte 5 [Reg97]148
Table A. 110. 10GBASE-R Test Pattern Seed a Byte 6 [Reg98]148
Table A. 111. 10GBASE-R Test Pattern Seed a Byte 7 [Reg99]149
Table A. 112. 10GBASE-R Test Pattern Seed B Byte 0 [Reg9A]149
Table A. 113. 10GBASE-R Test Pattern Seed B Byte 1 [Reg9B]149
Table A. 114. 10GBASE-R Test Pattern Seed B Byte 2 [Reg9C]149
Table A. 115. 10GBASE-R Test Pattern Seed B Byte 3 [Reg9D]149
Table A. 116. 10GBASE-R Test Pattern Seed B Byte 4 [Reg9E]149
Table A. 117. 10GBASE-R Test Pattern Seed B Byte 5 [Reg9F]149
Table A. 118. 10GBASE-R Test Pattern Seed B Byte 6 [Rega0]149
Table A. 119. 10GBASE-R Test Pattern Seed B Byte 7 [Rega1]149
Table A. 120. 10GBASE-R Test Pattern Control 0 [Rega2]150
Table A. 121. 10GBASE-R Test Pattern Control 1 [Rega3]150
Table A. 122. 10GBASE-R Test Pattern Error Counter Byte 0 [Rega4]151
Table A. 123. 10GBASE-R Test Pattern Error Counter Byte 1 [Rega5]151
Table A. 124. PMA Control [Regc6]151
Table A. 125. PMA Control [Regc7]151
Table A. 126. Loopback Mode Control [Rege0]152
Table A. 127. MPCS bist Control 0 [Rege1]152
Table A. 129. User Defined bist Constant 1 Byte_0 [Rege3]153
Table A. 130. User Defined bist Constant 1 Byte_1 [Rege4]153
Table A. 131. User Defined bist Constant 1 Msbyte [Rege5]153
Table A. 128. MPCS bist Control 1 [Rege2]153
Table A. 132. User Defined bist Constant 2 Byte_0 [Rege6]154
Table A. 133. User Defined bist Constant 2 Byte_1 [Rege7]154
Table A. 134. User Defined bist Constant 2 MSB [Rege8]154
Table A. 135. bist Status 0 [Rege9]154
Table A. 136. bist Status 1 [Regea]154
Table B. 1. 8B/10B Data Symbol Codes155
Appendix B. 8B/10B Symbol Coding155
Table B. 2. 8B/10B Control Symbol Codes160
Table C. 1. Recommended Parameters for Serdes PLL161
Appendix C. Calculating Parameters for Serdes PLL161
Table C. 2. Serial Protocol Applications166
Appendix D. Using Reveal Serdes Debug Tool167
References168
Technical Support Assistance169
Revision History170

Lattice Semiconductor CertusPro-NX - Architecture Overview; Device Architecture; Figure 5.1. Certuspro-NX 100 K Device Block Diagram

Table of Contents

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