Lattice Semiconductor CertusPro-NX Usage Guide

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
FPGA-TN-02245-0.81 © 2020-2021 Lattice Semiconductor 141
All rights reserved. CONFIDENTIAL
Table A. 57. Secondary Sync_Det Pattern Byte 0 [reg44]
Field
Name
Access
Width
Reset
Description
[7:0]
sec_sdptn_byte0
RW
8
8’h7c
Secondary Sync_Det Pattern Byte 0.
Table A. 58. Secondary Sync_Det Pattern Byte 1 [reg45]
Field
Name
Access
Width
Reset
Description
[7:0]
sec_sdptn_byte1
RW
8
8’h0
Secondary Sync_Det Pattern Byte 1.
Table A. 59. Secondary Sync_Det Pattern Byte 2 [reg46]
Field
Name
Access
Width
Reset
Description
[7:0]
sec_sdptn_byte2
RW
8
8’h0
Secondary Sync_Det Pattern Byte 2.
Table A. 60. Secondary Sync_Det Pattern Byte 3 [reg47]
Field
Name
Access
Width
Reset
Description
[7:0]
sec_sdptn_byte3
RW
8
8’h0
Secondary Sync_Det Pattern Byte 3.
Table A. 61. Secondary Sync_Det Pattern Byte MSB [reg48]
Field
Name
Access
Width
Reset
Description
[7:6]
sec_sdptn_byte3 [9:8]
RW
2
2’h0
Secondary Sync_Det Pattern MSB Register reflects the bits
9 to 8 of secondary Sync_Det pattern byte 3 to 0.
[5:4]
sec_sdptn_byte2 [9:8]
RW
2
2’h0
[3:2]
sec_sdptn_byte1 [9:8]
RW
2
2’h0
[1:0]
sec_sdptn_byte0 [9:8]
RW
2
2’h1
Table A. 62. Sync_Det Pattern Mask Code Byte 0 [reg49]
Field
Name
Access
Width
Reset
Description
[7:0]
sdptn_mask_byte0
RW
8
8’h7c
Sync_Det Pattern Mask Code Byte 0.
Table A. 63. Sync_Det Pattern Mask Code Byte 1 [reg4a]
Field
Name
Access
Width
Reset
Description
[7:0]
sdptn_mask_byte1
RW
8
8’h0
Sync_Det Pattern Mask Code Byte 1.
Table A. 64. Sync_Det Pattern Mask Code Byte 2 [reg4b]
Field
Name
Access
Width
Reset
Description
[7:0]
sdptn_mask_byte2
RW
8
8’h0
Sync_Det Pattern Mask Code Byte 2.
Table A. 65. Sync_Det Pattern Mask Code Byte 3 [reg4c]
Field
Name
Access
Width
Reset
Description
[7:0]
sdptn_mask_byte3
RW
8
8’h0
Sync_Det Pattern Mask Code Byte 3.
Table A. 66. Sync_Det Pattern Mask Code MSB [reg4d]
Field
Name
Access
Width
Reset
Description
[7:6]
sdptn_mask_byte3[9:8]
RW
2
2’h0
Sync_Det Pattern Mask Code MSB Register reflects the
bits 9 to 8 of Sync_Det pattern mask code byte 3 to 0.
[5:4]
sdptn_mask_byte2[9:8]
RW
2
2’h0
[3:2]
sdptn_mask_byte1[9:8]
RW
2
2’h0
[1:0]
sdptn_mask_byte0[9:8]
RW
2
2’h0

Lattice Semiconductor CertusPro-NX Specifications

General

Brand	Lattice Semiconductor
Model	CertusPro-NX
Category	Computer Hardware
Language	English