Lattice Semiconductor CertusPro-NX Usage Guide

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
78 © 2020-2021 Lattice Semiconductor FPGA-TN-02245-0.81
All rights reserved. CONFIDENTIAL
Quad 0
Floating
(internally gated)
Floating
(internally gated)
rx_lalign_clk_in[0]
tx_lalign_clk_in[0]
rx_lalign_clk_out[0]
tx_lalign_clk_out[0]
Tie High/Low
Tie High/Low
Figure 7.6. Single Quad Clock Connection
Clock Frequency
This section lists the recommended reference clock frequency, the PLL settings, PMA/PCS internal clock frequency,
interface data bus width and clock frequency for Ethernet, SLVS-EC, CoaXPress, DP/eDP and PCIe protocols. Refer to
Table 7.5 for the recommended settings for these protocols.
The PLL settings are the same for Tx PLL and Rx CDR, considering that the architecture of Tx PLL and Rx CDR is similar.
Refer to the SerDes (PMA) section for the Tx PLL and Rx CDR implementation details inside PMA channel.
Table 7.5. Recommend Settings for Some Protocols
Protocol
Rate
(Gbps)
F
Ref
(MHz)
PLL Setting
PMA Internal Clock
PMA
Output
PCS
Clk
Div
F
PCS
7
PCS
Bus
Width
Out
Clk
Div
F
OUT
8
User
Data
Bus
Width
M
1
F
2
N
3
F
VCO
4
F
bit
5
F
PMA
6
Ethernet
10GBASE-R
10.3125
161.1328
1
4
16
10312.5
10312.5
644.53
1
644.53
16
4
161.1328
64
QSGMII
5
125
2
4
10
10000
5000
500
2
250
20
2
125
40
XAUI
3.125
156.25
2
2
10
6250
3125
312.5
1
312.5
10
2
156.25
20
SGMII
1.25
125
8
1
10
10000
1250
125
1
125
10
1
125
10
1KBASE-X
1.25
125
8
1
10
10000
1250
125
1
125
10
1
125
10
SLVS-EC
Grade 3
5
9
—
2
4
10
~10000
~5000
~500
2
~250
20
2
~125
40
Grade 2
2.5
9
—
4
2
10
~10000
~2500
~250
1
~250
10
2
~125
20
Grade 1
1.25
9
—
8
1
10
~10000
~1250
~125
1
~125
10
1
~125
10
CoaXPress
—
6.25
156.25
1
2
20
6250
6250
312.5
1
312.5
20
2
156.25
40
—
5
125
2
4
10
10000
5000
500
2
250
20
2
125
40
—
3.125
156.25
2
2
10
6250
3125
312.5
1
312.5
10
2
156.25
20
—
2.5
125
4
2
10
10000
2500
250
1
250
10
2
125
20
—
1.25
125
8
1
10
10000
1250
125
1
125
10
1
125
10
DP/eDP
HBR3
8.1
135
1
3
20
8100
8100
405
1
405
20
2
202.5
40
HBR2
5.4
135
1
2
20
5400
5400
270
1
270
20
2
135
40
HBR
2.7
135
2
2
10
5400
2700
270
1
270
10
2
135
20
RBR
1.62
108
4
3
5
6480
1620
324
2
162
10
1
162
10
PCIe
Gen3
8
100
1
5
16
8000
8000
500
N/A
N/A
N/A
N/A
N/A
N/A
Gen2
5
100
2
5
10
10000
5000
500
N/A
N/A
N/A
N/A
N/A
N/A
Gen1
2.5
100
4
5
5
10000
2500
500
N/A
N/A
N/A
N/A
N/A
N/A
Notes:
M can be set as 1, 2, 4 and 8.
F can be set as 1, 2, 3, 4, 5 and 6.
N can be set as 5, 8, 10, 16 and 20.
F
VCO
=F
Ref
*M*F*N
F
bit
=F
Ref
*F*N
F
PMA
=F
Ref
*F
F
PCS
presents the clock frequency of tx_pcs_clk and rx_pcs_clk.
F
OUT
presents the clock frequency of tx_out_clk and rx_out_clk.
The setting in this row is applicable to the whole range of this baud rate. The actual bit rate is determined by the reference
clock, which can vary in a small range.

Lattice Semiconductor CertusPro-NX Specifications

General

Brand	Lattice Semiconductor
Model	CertusPro-NX
Category	Computer Hardware
Language	English