CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
FPGA-TN-02245-0.81 © 2020-2021 Lattice Semiconductor 117
All rights reserved. CONFIDENTIAL
field lalign_ptn_len in Table A. 67.
Maximum Lane-to-Lane Skew
Specifies the maximum lane-to-lane skew in byte. For more details, refer to register field
max_lskew in Table A. 68.
Primary Lane Alignment Pattern
Byte 0
Specifies the primary pattern Byte 0 in hex form for Lane Alignment.
Primary Lane Alignment Pattern
Byte 1
Specifies the primary pattern Byte 1 in hex form for Lane Alignment.
Primary Lane Alignment Pattern
Byte 2
Specifies the primary pattern Byte 2 in hex form for Lane Alignment.
Primary Lane Alignment Pattern
Byte 3
Specifies the primary pattern Byte 3 in hex form for Lane Alignment.
Specifies whether Secondary Lane Alignment is enabled or not.
Near End Parallel Loopback
Far End Parallel Loopback
Primitive
Table 14.4 shows the pin-to-pin connection between CertusPro-NX SerDes/PCS primitive and MPCS foundational IP.
Table 14.4. Pin-to-Pin Connection
MPCS Foundational IP Port –
MPCS/EPCS
MPCS Foundational IP Port – PIPE
mpcs_clkin_i/
epcs_clkin_i
mpcs_tx_usr_clk_i/
epcs_tx_usr_clk_i
mpcs_rx_usr_clk_i/
epcs_rx_usr_clk_i
CH[3:0]_PIPE_PCS_TXCLKOUT
mpcs_tx_out_clk_o/
epcs_tx_clk_o
mpcs_rx_out_clk_o/
epcs_rx_clk_o
mpcs_perstn_i/
epcs_rstn_i
mpcs_tx_pcs_rstn_i/
epcs_tx_pcs_rstn_i
mpcs_rx_pcs_rstn_i/
epcs_rx_pcs_rstn_i
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