CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
FPGA-TN-02245-0.81 © 2020-2021 Lattice Semiconductor 29
All rights reserved. CONFIDENTIAL
switch back to the process of frequency lock acquisition.
This signal is used to request a Figure of Merit (FOM)
evaluation.
This signal is used to handshake the FOM evaluation request in
MPCS mode. It is asserted for a single clock cycle by the PMA
Controller. This signal is synchronous to mpcs_tx_out_clk_o.
This signal is the evaluated FOM result. This signal is
synchronous to mpcs_tx_out_clk_o.
MPCS rates:
2’b10 – Rate2
2’b01 – Rate1
2’b00 – Rate0
MPCS current speeds:
2’b10 – Rate2
2’b01 – Rate1
2’b00 – Rate0
PHY transmit valid: this signal is used to transmit valid data. If
deasserted, the PMA macro is put in Electrical Idle 1. It can be
used for protocol requiring Electrical Idle SATA and must also be
deasserted as long as mpcs_ready_o is not asserted. This signal
is also required to be generated one clock cycle earlier than the
corresponding mpcs_tx_data_i signals.
mpcs_txval_i = 0 causes the PMA Tx driver to generate the
Electrical Idle condition 22 tx_pcs_clk cycles later. If
mpcs_txval_i = 1, this operation causes the PMA Tx driver to
exit Electrical Idle condition 22 tx_pcs_clk cycles later.
PHY receive valid: this signal is used to signal receive valid data.
It corresponds to the two condition completed by the PMA
control logic:
Receiver detects incoming data (not in Electrical Idle);
CDR PLL is locked to input bitstream in fine grain state.
When asserted, this signal tells you that the PHY is ready to
transmit while using mpcs_txval_i.
PHY ready: this signal is asserted when the PHY has completed
the calibration sequence for each specific lane. This signal is
driven by mpcs_clkin_i.
This signal configure the activity detector to detect out-of-band
(OOB) accurately.
When asserted high, programmed de-emphasis is applied to the
transmitter driver.
This signal is used to report the PHY current power state. This
signal is driven by mpcs_clkin_i.
PIPE control to skip 1 bit on receiver. When asserted, this causes
the receiver to freeze 1-bit clock. This function can be used to
control word alignment. This signal is considered as
asynchronous clock.
EPCS Interface
EPCS interface is accessible when SerDes/PCS is configured as PMA only mode. EPCS mode is designed for applications
that do not need encoding and decoding. Table 5.8 shows the detailed EPCS interface descriptions. All the signals listed
in this table are per lane, and NL means the number of lanes.
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