Lattice Semiconductor CertusPro-NX Usage Guide

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
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All rights reserved. CONFIDENTIAL
Character deleting occurs, if the number of data residing in Rx FIFO exceeds high water line. Character inserting occurs,
if the number of data residing in Rx FIFO is lower than low water line.
Idle control character (/I/) deleting/inserting rules include:
 /I/s are inserted or deleted in groups of 4.
 /I/s may be added following idle or ordered sets.
 /I/s shall not be added while data is being received.
 When deleting /I/s, the first four characters after a /T/ cannot be deleted.
The Sequence ordered sets (/O/) deleting rules include:
 Only Sequence ordered-set can be deleted.
 Deleting only when two consecutive sequence ordered sets are received; and only one of the two consecutive
sequence ordered set can be deleted.
 Signal ordered sets are not deleted for clock compensation.
Block Aligner
The Block Aligner module detects the boundary of a 66-bit data block received from Rx Gear Box. The incoming 66-bit
data stream is slipped one bit at a time until the required number of valid synchronization header (bit 0 and bit 1) is
detected in the received data stream.
This module implements block lock FSM specified in Clause 49 of IEEE802.3, which shifts the incoming data stream and
detects the block boundary. The bit number of shifting can be checked via related status registers. The block lock is
achieved when rx_blk_lock signal is driven high.
This module can optionally be bypassed for test purpose.
BER Monitor
The BER Monitor module is implemented in accordance with the 10GBASE-R protocol specified by IEEE802.3. The BER
Monitor starts to count the number of invalid synchronization headers within a 125-μs period.
If more than 16 invalid synchronization headers are observed in a 125-μs period, the BER Monitor asserts the hi_ber
signal, indicating a high bit error ratio condition. The BER Monitor counts the number of times the BER FSM has
entered the BER_BAD_SH state, and the number of times the BER FSM has entered the RX_E state. These counter
values can be checked via 10GBASE-R BER Counter register.
Note:
The BER_BAD_SH state and RX_E state are defined by IEEE802.3
PMA Only Mode
In this mode, the PMA EPCS data bus is accessed by user logic with very low latency. Only Tx/Rx FIFO and Tx
Lane-to-lane Deskew modules are between the PMA Controller and fabric. Figure 6.30 is the block diagram of PMA
Only mode.
The functionality of these three modules in PMA Only mode are the same as those in 8B/10B PCS mode. Check the
Function Block Description section for detailed function descriptions about these modules.

Lattice Semiconductor CertusPro-NX Specifications

General

Brand	Lattice Semiconductor
Model	CertusPro-NX
Category	Computer Hardware
Language	English