CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
42 © 2020-2021 Lattice Semiconductor FPGA-TN-02245-0.81
All rights reserved. CONFIDENTIAL
MPCS Mode
Protocol != “10GE”
MPCS Mode
Protocol == “10GE”
8-bit control indication.
bit[0] is the control signal for
rx_data_64b[7:0];
bit[1] is the control signal for
rx_data_64b[15:8];
…
bit[7] is the control signal for
rx_data_64b[63:56].
In 64B/66B decoder bypass mode,
the bit [1:0] of this signal is used to
carry "rx_header[1:0]" of a 66-bit
block. Other bits are not used in this
mode.
mpcs_rx_ch_dout_o[73:72]/
epcs_rxdata_o[73:72]
rx_fifo_add[1:0]
The indication of insertion for clock
frequency difference compensation.
bit[1] corresponds to 4-byte
idles which are carried by
bit[63:32] of data bus
(rx_data_64b).
bit[0] corresponds to 4-byte
idles which are carried by
bit[31:0] of data bus
(rx_data_64b).
mpcs_rx_ch_dout_o[75:74]/
epcs_rxdata_o[75:74]
rx_fifo_del[1:0]
The indication of deletion for clock
frequency difference compensation.
bit[1] corresponds to 4-byte
idles or sequence ordered-set
which are carried by bit[63:32]
of data bus (rx_data_64b).
bit[0] corresponds to 4-byte
idles or sequence ordered-set
which are carried by bit[31:0] of
data bus (rx_data_64b).
mpcs_rx_ch_dout_o[78:76]/
epcs_rxdata_o[78:76]
mpcs_rx_ch_dout_o[79]/
epcs_rxdata_o[79]
rx_data_valid
1: the output data is valid.
0: no valid data on the output of
RX FIFO.
rx_fifo_status[3:0]
bit[0]: FIFO is almost empty.
bit[1]: FIFO is almost full.
bit[2]: FIFO underflow.
bit[3]: FIFO overflow.
rx_fifo_status[3:0]
bit[0]: Reserved.
bit[1]: Reserved.
bit[2]: FIFO underflow.
bit[3]: FIFO overflow.
rx_fifo_status[3:0]
bit[0]:
Reserved.
bit[1]:
Reserved.
bit[2]: FIFO
underflow.
bit[3]: FIFO
overflow.
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