ARTERY AT32F421C8T7 - Programmable Data Transfer Width; Figure 9-3 PWIDTH: Byte, MWIDTH: Half-Word; Figure 9-4 PWIDTH: Half-Word, MWIDTH: Word; Figure 9-5 PWIDTH: Word, MWIDTH: Byte

AT32F421 Series Reference Manual
2022.11.11 Page 100 Rev 2.02
9.3.4 Programmable data transfer width
Transfer width of the source data and destination data is programmable through the PWIDTH and
MWIDTH bits in the DMA_CxCTRL register. When PWIDTH is not equal to MWIDTH, number of data to
be transferred can be aligned according to the settings of PWIDTH/MWIDTH.
Figure 9-3 PWIDTH: byte, MWIDTH: half-word
B3 B2
B1 B0
Half-word3
Half-word2
Half-word1
Half-word0
4
th
3
rd
2
nd
1
st
B3 B2 B1 B0
4
th
3
rd
2
nd
1
st
HW3 HW2 HW1 HW0
AHB Read Sequence AHB Write Sequence
Figure 9-4 PWIDTH: half-word, MWIDTH: word
B7 B5
B6 B4
B3 B1
B2 B0
word3
word2
word1
word0
4
th
3
rd
2
nd
1
st
HW3 HW2 HW1 HW0
4
th
3
rd
2
nd
1
st
W3 W2 W1 W0
AHB Read Sequence AHB Write Sequence
Figure 9-5 PWIDTH: word, MWIDTH: byte
BF BB
BE BA
B7 B3
B6 B2
BD B9
BC B8
B5 B1
B4 B0
Byte3
Byte2
Byte1
Byte0
4
th
3
rd
2
nd
1
st
W3 W2 W1 W0
4
th
3
rd
2
nd
1
st
B3 B2 B1 B0
AHB Read Sequence AHB Write Sequence